Patents by Inventor Kazuyuki Kouno
Kazuyuki Kouno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11615299Abstract: A neural network computation circuit that outputs output data according to a result of a multiply-accumulate operation between input data and connection weight coefficients, the neural network computation circuit includes computation units in each of which a memory element and a transistor are connected in series between data lines, a memory element and a transistor are connected in series between data lines, and gates of the transistors are connected to word lines. The connection weight coefficients are stored into the memory elements. A word line selection circuit places the word lines in a selection state or a non-selection state according to the input data. A determination circuit determines current values flowing in data lines to output output data. A current application circuit has a function of adjusting current values flowing in data lines, and adjusts connection weight coefficients without rewriting the memory elements.Type: GrantFiled: March 4, 2020Date of Patent: March 28, 2023Assignee: PANASONIC HOLDINGS CORPORATIONInventors: Reiji Mochida, Kazuyuki Kouno, Yuriko Hayata, Takashi Ono, Masayoshi Nakayama
-
Patent number: 11604974Abstract: A neural network computation circuit that outputs output data according to a result of a multiply-accumulate operation between input data and connection weight coefficients, the neural network computation circuit includes computation units in each of which a non-volatile semiconductor memory element and a cell transistor are connected in series between data lines, a non-volatile semiconductor memory element and a cell transistor are connected in series between data lines, and gates of the transistors are connected to word lines. The connection weight coefficients are stored into the non-volatile semiconductor memory elements. A word line selection circuit places the word lines in a selection state or a non-selection state according to the input data. A determination circuit determines current values flowing in data lines to output output data.Type: GrantFiled: March 3, 2020Date of Patent: March 14, 2023Assignee: PANASONIC HOLDINGS CORPORATIONInventors: Kazuyuki Kouno, Takashi Ono, Masayoshi Nakayama, Reiji Mochida, Yuriko Hayata
-
Patent number: 11495289Abstract: Connection weight coefficients to be used in a neural network computation are stored in a memory array. A word line drive circuit drives a word line corresponding to input data of a neural network. A column selection circuit connects to a computation circuit bit lines to which a connection weight coefficient to be computed is connected. The computation circuit determines the sum of cell currents flowing in the bit lines. A result of the determination made by the computation circuit is stored in an output holding circuit, and is set as an input of a neural network in the next layer, to the word line drive circuit. A control circuit instructs the word line drive circuit and the column selection circuit to select the word line and the bit line to be used in the neural network computation, based on information held in a network configuration information holding circuit.Type: GrantFiled: March 4, 2020Date of Patent: November 8, 2022Assignee: PANASONIC HOLDINGS CORPORATIONInventors: Yuriko Hayata, Kazuyuki Kouno, Masayoshi Nakayama, Reiji Mochida, Takashi Ono, Hitoshi Suwa
-
Patent number: 11354569Abstract: A neural network computation circuit includes in-area multiple-word line selection circuits that are provided in one-to-one correspondence to a plurality of word line areas into which a plurality of word lines included in a memory array are logically divided. Each of the in-area multiple-word line selection circuits sets one or more word lines in a selected state or a non-selected state, and includes a first latch and a second latch provided for each word line.Type: GrantFiled: March 2, 2020Date of Patent: June 7, 2022Assignee: PANASONIC CORPORATIONInventors: Masayoshi Nakayama, Kazuyuki Kouno, Yuriko Hayata, Takashi Ono, Reiji Mochida
-
Patent number: 11062772Abstract: A variable resistance non-volatile memory device includes a memory cell array including memory cells, a write circuit, and a control circuit. Each memory cell includes a memory element that is a non-volatile and variable-resistance memory element, and a cell transistor. The write circuit includes a source line driver circuit connected to the cell transistor and a bit line driver circuit connected to the memory element. When performing a write operation of changing the memory element to a low resistance state, the control circuit performs control for allowing current having a first current value to flow through the memory element, and subsequently performs control for allowing current having a second current value to flow through the memory element. The second current value is greater than the largest value of overshoot current flowing through the memory element after the start of the changing of the memory element to the low resistance state.Type: GrantFiled: December 5, 2018Date of Patent: July 13, 2021Assignee: PANASONIC CORPORATIONInventors: Reiji Mochida, Kazuyuki Kouno, Takashi Ono, Masayoshi Nakayama, Yuriko Hayata
-
Publication number: 20210065795Abstract: A variable resistance non-volatile memory device includes a memory cell array including memory cells, a write circuit, and a control circuit. Each memory cell includes a memory element that is a non-volatile and variable-resistance memory element, and a cell transistor. The write circuit includes a source line driver circuit connected to the cell transistor and a bit line driver circuit connected to the memory element. When performing a write operation of changing the memory element to a low resistance state, the control circuit performs control for allowing current having a first current value to flow through the memory element, and subsequently performs control for allowing current having a second current value to flow through the memory element. The second current value is greater than the largest value of overshoot current flowing through the memory element after the start of the changing of the memory element to the low resistance state.Type: ApplicationFiled: December 5, 2018Publication date: March 4, 2021Inventors: Reiji MOCHIDA, Kazuyuki KOUNO, Takashi ONO, Masayoshi NAKAYAMA, Yuriko HAYATA
-
Publication number: 20200202925Abstract: Connection weight coefficients to be used in a neural network computation are stored in a memory array. A word line drive circuit drives a word line corresponding to input data of a neural network. A column selection circuit connects to a computation circuit bit lines to which a connection weight coefficient to be computed is connected. The computation circuit determines the sum of cell currents flowing in the bit lines. A result of the determination made by the computation circuit is stored in an output holding circuit, and is set as an input of a neural network in the next layer, to the word line drive circuit. A control circuit instructs the word line drive circuit and the column selection circuit to select the word line and the bit line to be used in the neural network computation, based on information held in a network configuration information holding circuit.Type: ApplicationFiled: March 4, 2020Publication date: June 25, 2020Inventors: Yuriko HAYATA, Kazuyuki KOUNO, Masayoshi NAKAYAMA, Reiji MOCHIDA, Takashi ONO, Hitoshi SUWA
-
Publication number: 20200202204Abstract: A neural network computation circuit that outputs output data according to a result of a multiply-accumulate operation between input data and connection weight coefficients, the neural network computation circuit includes computation units in each of which a non-volatile semiconductor memory element and a cell transistor are connected in series between data lines, a non-volatile semiconductor memory element and a cell transistor are connected in series between data lines, and gates of the transistors are connected to word lines. The connection weight coefficients are stored into the non-volatile semiconductor memory elements. A word line selection circuit places the word lines in a selection state or a non-selection state according to the input data. A determination circuit determines current values flowing in data lines to output output data.Type: ApplicationFiled: March 3, 2020Publication date: June 25, 2020Inventors: Kazuyuki KOUNO, Takashi ONO, Masayoshi NAKAYAMA, Reiji MOCHIDA, Yuriko HAYATA
-
Publication number: 20200202203Abstract: A neural network computation circuit includes in-area multiple-word line selection circuits that are provided in one-to-one correspondence to a plurality of word line areas into which a plurality of word lines included in a memory array are logically divided. Each of the in-area multiple-word line selection circuits sets one or more word lines in a selected state or a non-selected state, and includes a first latch and a second latch provided for each word line.Type: ApplicationFiled: March 2, 2020Publication date: June 25, 2020Inventors: Masayoshi NAKAYAMA, Kazuyuki KOUNO, Yuriko HAYATA, Takashi ONO, Reiji MOCHIDA
-
Publication number: 20200202207Abstract: A neural network computation circuit that outputs output data according to a result of a multiply-accumulate operation between input data and connection weight coefficients, the neural network computation circuit includes computation units in each of which a memory element and a transistor are connected in series between data lines, a memory element and a transistor are connected in series between data lines, and gates of the transistors are connected to word lines. The connection weight coefficients are stored into the memory elements. A word line selection circuit places the word lines in a selection state or a non-selection state according to the input data. A determination circuit determines current values flowing in data lines to output output data. A current application circuit has a function of adjusting current values flowing in data lines, and adjusts connection weight coefficients without rewriting the memory elements.Type: ApplicationFiled: March 4, 2020Publication date: June 25, 2020Inventors: Reiji MOCHIDA, Kazuyuki KOUNO, Yuriko HAYATA, Takashi ONO, Masayoshi NAKAYAMA
-
Patent number: 10573810Abstract: A semiconductor memory device includes a first select line and a second select line. A first memory element among a plurality of memory elements has a first top electrode and a first bottom electrode. The first top electrode is connected to the first select line and the first bottom electrode is connected to the second select line. A second memory element among the plurality of memory elements, which is disposed adjacent to the first memory element, has a second top electrode and a second bottom electrode. The second top electrode is connected to the first select line, and the second bottom electrode is connected to the first select line without passing a resistive element of a memory element other than the second memory element.Type: GrantFiled: October 30, 2017Date of Patent: February 25, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Yoshiaki Nakao, Kazuyuki Kouno
-
Publication number: 20180069177Abstract: A semiconductor memory device includes a first select line and a second select line. A first memory element among a plurality of memory elements has a first top electrode and a first bottom electrode. The first top electrode is connected to the first select line and the first bottom electrode is connected to the second select line. A second memory element among the plurality of memory elements, which is disposed adjacent to the first memory element, has a second top electrode and a second bottom electrode. The second top electrode is connected to the first select line, and the second bottom electrode is connected to the first select line without passing a resistive element of a memory element other than the second memory element.Type: ApplicationFiled: October 30, 2017Publication date: March 8, 2018Inventors: Yoshiaki NAKAO, Kazuyuki KOUNO
-
Patent number: 9747979Abstract: A memory array includes a plurality of memory cells arranged in a matrix, each memory cell including a cell transistor and a variable resistance element connected to an end of the cell transistor, and a cell transistor performance measuring cell including a MOS transistor. The cell transistor performance measuring cell is used to stabilize resistance values in a low resistance state and a high resistance state of the variable resistance element irrespective of variations in the cell transistor and thereby improve read characteristics and reliability characteristics of a nonvolatile semiconductor storage device.Type: GrantFiled: August 13, 2015Date of Patent: August 29, 2017Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Masayoshi Nakayama, Kazuyuki Kouno, Reiji Mochida, Keita Takahashi
-
Patent number: 9478283Abstract: A nonvolatile semiconductor memory device includes: a memory cell (MC0) including a cell transistor (TC0) and a variable resistance element (RR0); a memory cell (MC1) including a cell transistor (TC1) and a variable resistance element (RR1); a word line (WL0) connected to the cell transistor (TC0); a word line (WL1) connected to the cell transistor (TC1); a data line (SL0) connecting the cell transistor (TC0) and the variable resistance element (RR1) to each other; and a data line (BL0) connecting the variable resistance element (RR0) and the cell transistor (TC1) to each other.Type: GrantFiled: November 19, 2013Date of Patent: October 25, 2016Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Reiji Mochida, Kazuyuki Kouno
-
Patent number: 9343115Abstract: A memory array includes a resistive memory cell array having a first cell transistor and a resistance change element connected in series and a reference cell array having a second cell transistor and a resistance element connected in series. The second cell transistor of the reference cell array is connected to a reference source line, and the resistance element is connected to a reference bit line. A dummy memory cell is connected to the reference bit line in the memory cell array, and both ends of a resistance change element of the dummy memory cell are short-circuited through the reference bit line.Type: GrantFiled: March 12, 2015Date of Patent: May 17, 2016Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Takanori Ueda, Kazuyuki Kouno, Yasuo Murakuki, Masayoshi Nakayama, Yuriko Ishitobi, Keita Takahashi
-
Patent number: 9230640Abstract: A memory cell array includes a plurality of word lines each connected to gates of cell transistors in corresponding ones of a plurality of memory cells, a plurality of first control lines, a plurality of second control lines, a first ground circuit configured to ground the first control lines together in accordance with a first signal, and the first ground circuit includes a plurality of first transistors provided in a one-to-one correspondence with the first control lines, and each including a drain connected to a corresponding one of the first control lines, a first ground line configured to ground sources of the first transistors together, and a first signal line connected to gates of the first transistors to feed the first signal to the gates.Type: GrantFiled: December 6, 2013Date of Patent: January 5, 2016Assignee: Panasonic CorporationInventors: Takanori Ueda, Kazuyuki Kouno
-
Publication number: 20150348626Abstract: A memory array includes a plurality of memory cells arranged in a matrix, each memory cell including a cell transistor and a variable resistance element connected to an end of the cell transistor, and a cell transistor performance measuring cell including a MOS transistor. The cell transistor performance measuring cell is used to stabilize resistance values in a low resistance state and a high resistance state of the variable resistance element irrespective of variations in the cell transistor and thereby improve read characteristics and reliability characteristics of a nonvolatile semiconductor storage device.Type: ApplicationFiled: August 13, 2015Publication date: December 3, 2015Inventors: Masayoshi NAKAYAMA, Kazuyuki KOUNO, Reiji MOCHIDA, Keita TAKAHASHI
-
Patent number: 9190117Abstract: A nonvolatile semiconductor memory device includes: a memory cell array having a plurality of memory cells arranged in a matrix; a reference bit line; a reference source line; at least one reference cell including first and second transistors serially connected between these lines; a reference word line connected to the gate of the first transistor; and a reference driver circuit configured to control the gate voltage of the second transistor.Type: GrantFiled: July 24, 2014Date of Patent: November 17, 2015Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Takanori Ueda, Kazuyuki Kouno
-
Patent number: 9153625Abstract: A non-volatile semiconductor memory device includes a plurality of series-coupled fixed resistance elements, a plurality of reference cell transistors, and reference word lines coupled to gates of the reference cell transistors, a first reference data line coupled to one end of a resistance path in which a plurality of fixed resistance elements are arranged, and a second reference data line coupled in common to one ends of the reference cell transistors. The other end of each of the reference cell transistors is coupled to one of coupling points of the fixed resistance elements or the other end of the resistance path.Type: GrantFiled: July 24, 2014Date of Patent: October 6, 2015Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Kazuyuki Kouno, Takanori Ueda
-
Publication number: 20150279457Abstract: A nonvolatile semiconductor memory device includes: a memory cell (MC0) including a cell transistor (TC0) and a variable resistance element (RR0); a memory cell (MC1) including a cell transistor (TC1) and a variable resistance element (RR1); a word line (WL0) connected to the cell transistor (TC0); a word line (WL1) connected to the cell transistor (TC1); a data line (SL0) connecting the cell transistor (TC0) and the variable resistance element (RR1) to each other; and a data line (BL0) connecting the variable resistance element (RR0) and the cell transistor (TC1) to each other.Type: ApplicationFiled: November 19, 2013Publication date: October 1, 2015Applicant: Panasonic Intellectual Property Management Co., Ltd.Inventors: Reiji Mochida, Kazuyuki Kouno