Patents by Inventor Kazuyuki Nakagawa

Kazuyuki Nakagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9837369
    Abstract: In a semiconductor device (SP1) according to an embodiment, a solder resist film (first insulating layer, SR1) which is in contact with the base material layer, and a resin body (second insulating layer, 4) which is in contact with the solder resist film and the semiconductor chip, are laminated in between the base material layer (2CR) of a wiring substrate 2 and a semiconductor chip (3). In addition, a linear expansion coefficient of the solder resist film is equal to or larger than a linear expansion coefficient of the base material layer, and the linear expansion coefficient of the solder resist film is equal to or smaller than a linear expansion coefficient of the resin body. Also, the linear expansion coefficient of the base material layer is smaller than the linear expansion coefficient of the resin body. According to the above-described configuration, damage of the semiconductor device caused by a temperature cyclic load can be suppressed, and thereby reliability can be improved.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: December 5, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshikazu Shimote, Shinji Baba, Toshihiro Iwasaki, Kazuyuki Nakagawa
  • Publication number: 20170180629
    Abstract: In an focus control apparatus, a focus detection unit detects a defocus value, a control unit controls focus position adjustment, a first acquisition unit acquires reliability of the defocus value, a storage unit stores images captured by an image sensor at an in-focus position based on the defocus value and other focus positions and the defocus value detected for each image, in association with each image, and a second acquisition unit acquires a first correction value to be used for correcting the focus position adjustment based on the defocus values of unselected images in a case where the reliability of the defocus value corresponding to a selected image is lower than a first threshold, wherein The control unit adjusts the focus position using the first correction value.
    Type: Application
    Filed: December 20, 2016
    Publication date: June 22, 2017
    Inventors: Hiroshi Abe, Kazuyuki Nakagawa
  • Publication number: 20170092614
    Abstract: The joint reliability in flip chip bonding of a semiconductor device is enhanced. Prior to flip chip bonding, flux 9 is applied to the solder bumps 5a for flip chip bonding over a substrate and reflow/cleaning is carried out and then flip chip bonding is carried out. This makes is possible to thin the oxide film over the surfaces of the solder bumps 5a and make the oxide film uniform. As a result, it is possible to suppress the production of local solder protrusions to reduce the production of solder bridges during flip chip bonding and enhance the joint reliability in the flip chip bonding of the semiconductor device.
    Type: Application
    Filed: December 9, 2016
    Publication date: March 30, 2017
    Inventors: Toshihiro IWASAKI, Takeumi KATO, Takanori OKITA, Yoshikazu SHIMOTE, Shinji BABA, Kazuyuki NAKAGAWA, Michitaka KIMURA
  • Publication number: 20170033038
    Abstract: A semiconductor device includes a wiring substrate including wiring layers, a semiconductor chip including electrode pads and mounted on the wiring substrate, and a first capacitor including a first electrode and a second electrode, and mounted on the wiring substrate. The wiring layers include a first wiring layer including a first terminal pad electrically connected with the first electrode of the first capacitor and a second terminal pad electrically connected with the second electrode of the first capacitor; and a second wiring layer on an inner side by one layer from the first wiring layer of the wiring substrate and including a first conductor pattern having a larger area than each of the first terminal pad and the second terminal pad. The first conductor pattern includes a first opening in a region overlapping with each of the first terminal pad and the second terminal pad in the second wiring layer.
    Type: Application
    Filed: April 24, 2014
    Publication date: February 2, 2017
    Inventors: Kazuyuki NAKAGAWA, Shinji BABA, Takeumi KATO
  • Publication number: 20160234426
    Abstract: In an image capturing apparatus that sequentially photographs a plurality of images by changing a focus position of a lens unit by a predetermined amount, a display area is selected according to a ratio of a vertical line component to a horizontal line component of a main subject for each of the plurality of images photographed by the image capturing apparatus. A display unit displays a plurality of display areas corresponding to the focus detection area selected by the selection unit, by arranging the plurality of display areas side by side.
    Type: Application
    Filed: February 8, 2016
    Publication date: August 11, 2016
    Inventor: Kazuyuki Nakagawa
  • Publication number: 20160233189
    Abstract: In a semiconductor device (SP1) according to an embodiment, a solder resist film (first insulating layer, SR1) which is in contact with the base material layer, and a resin body (second insulating layer, 4) which is in contact with the solder resist film and the semiconductor chip, are laminated in between the base material layer (2CR) of a wiring substrate 2 and a semiconductor chip (3). In addition, a linear expansion coefficient of the solder resist film is equal to or larger than a linear expansion coefficient of the base material layer, and the linear expansion coefficient of the solder resist film is equal to or smaller than a linear expansion coefficient of the resin body. Also, the linear expansion coefficient of the base material layer is smaller than the linear expansion coefficient of the resin body. According to the above-described configuration, damage of the semiconductor device caused by a temperature cyclic load can be suppressed, and thereby reliability can be improved.
    Type: Application
    Filed: September 27, 2013
    Publication date: August 11, 2016
    Applicant: Renesas Electronics Corporation
    Inventors: Yoshikazu SHIMOTE, Shinji BABA, Toshihiro IWASAKI, Kazuyuki NAKAGAWA
  • Patent number: 9330992
    Abstract: A semiconductor device is provided with improved resistance to noise. Conductive planes are respectively formed over wiring layers. One wiring layer is provided with a through hole land integrally formed with a through hole wiring. In other wiring layers located over the wiring layer with the through hole land, openings are respectively formed in the conductive planes. The area of each of the openings is larger than the plane area of the through hole land.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: May 3, 2016
    Assignee: Renesas Electronics Corporation
    Inventor: Kazuyuki Nakagawa
  • Publication number: 20160111388
    Abstract: A technique capable of improving reliability of a semiconductor device is provided. In the present invention, as a wiring board on which a semiconductor chip is mounted, a build-up wiring board is not used but a through wiring board THWB is used. In this manner, in the present invention, the through wiring board formed of only a core layer is used, so that it is not required to consider a difference in thermal expansion coefficient between a build-up layer and the core layer, and besides, it is not required either to consider the electrical disconnection of a fine via formed in the build-up layer because the build-up layer does not exist. As a result, according to the present invention, the reliability of the semiconductor device can be improved while a cost is reduced.
    Type: Application
    Filed: December 30, 2015
    Publication date: April 21, 2016
    Inventors: Shinji Baba, Masaki Watanabe, Muneharu Tokunaga, Kazuyuki Nakagawa
  • Patent number: 9293405
    Abstract: A technique capable of improving reliability of a semiconductor device is provided. In the present invention, as a wiring board on which a semiconductor chip is mounted, a build-up wiring board is not used but a through wiring board THWB is used. In this manner, in the present invention, the through wiring board formed of only a core layer is used, so that it is not required to consider a difference in thermal expansion coefficient between a build-up layer and the core layer, and besides, it is not required either to consider the electrical disconnection of a fine via formed in the build-up layer because the build-up layer does not exist. As a result, according to the present invention, the reliability of the semiconductor device can be improved while a cost is reduced.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: March 22, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Shinji Baba, Masaki Watanabe, Muneharu Tokunaga, Kazuyuki Nakagawa
  • Patent number: 9023717
    Abstract: To provide a semiconductor device having improved reliability. A method of manufacturing a semiconductor device according to one embodiment includes a step of cutting, in a dicing region arranged between two chip regions adjacent to each other, a wafer along an extending direction of the dicing region. The dicing region has therein a plurality of metal patterns in a plurality of columns. In the step of cutting the wafer, one or more of the columns of metal patterns formed in a plurality of columns are removed, and the metal patterns of the column(s) different from the above-mentioned one or more of the columns are not removed.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: May 5, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuyuki Nakagawa, Shunichi Abe
  • Patent number: 8994844
    Abstract: An image processing apparatus that can reduce the area where acquired images are held and reduce the load in image synthesis when successive images are to be generated. Acquired images are sequentially acquired and held in an acquired image storage circuit. A first set number of acquired images among the acquired images are synthesized to generate first composite images. The first composite images are held in a grouped image storage circuit. Second composite images from an image generated last to an image corresponding to a second set number among the first composite images are synthesized to generate a second composite image. The acquired images used to generate the first composite images are sequentially deleted.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: March 31, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kazuyuki Nakagawa
  • Publication number: 20150079762
    Abstract: To provide a semiconductor device having improved reliability. A method of manufacturing a semiconductor device according to one embodiment includes a step of cutting, in a dicing region arranged between two chip regions adjacent to each other, a wafer along an extending direction of the dicing region. The dicing region has therein a plurality of metal patterns in a plurality of columns. In the step of cutting the wafer, one or more of the columns of metal patterns formed in a plurality of columns are removed, and the metal patterns of the column(s) different from the above-mentioned one or more of the columns are not removed.
    Type: Application
    Filed: September 12, 2014
    Publication date: March 19, 2015
    Inventors: Kazuyuki NAKAGAWA, Shunichi ABE
  • Publication number: 20140252612
    Abstract: A semiconductor device is provided with improved resistance to noise. Conductive planes are respectively formed over wiring layers. One wiring layer is provided with a through hole land integrally formed with a through hole wiring. In other wiring layers located over the wiring layer with the through hole land, openings are respectively formed in the conductive planes. The area of each of the openings is larger than the plane area of the through hole land.
    Type: Application
    Filed: March 4, 2014
    Publication date: September 11, 2014
    Applicant: Renesas Electronics Corporation
    Inventor: Kazuyuki NAKAGAWA
  • Publication number: 20140008798
    Abstract: A technique capable of improving reliability of a semiconductor device is provided. In the present invention, as a wiring board on which a semiconductor chip is mounted, a build-up wiring board is not used but a through wiring board THWB is used. In this manner, in the present invention, the through wiring board formed of only a core layer is used, so that it is not required to consider a difference in thermal expansion coefficient between a build-up layer and the core layer, and besides, it is not required either to consider the electrical disconnection of a fine via formed in the build-up layer because the build-up layer does not exist. As a result, according to the present invention, the reliability of the semiconductor device can be improved while a cost is reduced.
    Type: Application
    Filed: March 22, 2011
    Publication date: January 9, 2014
    Inventors: Shinji Baba, Masaki Watanabe, Muneharu Tokunaga, Kazuyuki Nakagawa
  • Patent number: 8580620
    Abstract: To aim at improvement of reliability of a semiconductor device of flip chip connection type. In assembling a BGA of flip chip connection type, when a semiconductor chip is solder-connected by a flip chip connection, because solder precoat is formed on the surface of a land on the side of an undersurface of a wiring substrate, the connection between the land and a solder ball, which is an external terminal, is solder-connection, and therefore, it is possible to increase impact resistance of a connection part between the land and the solder ball and to aim at improvement of reliability of the BGA.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: November 12, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuyuki Nakagawa, Shinji Baba, Satoshi Yamada, Takashi Karashima
  • Patent number: 8446501
    Abstract: The image pickup apparatus includes an image pickup element 106 including image pickup pixels photoelectrically converting an object image formed by a light flux from an image pickup optical system 202 and focus detection pixels photoelectrically converting two images formed by two divided light fluxes of the light flux from the image pickup optical system. The apparatus further includes an image generator 112 generating an image based on first pixel signals, a focus controller 112 performing focus control for the image pickup optical system based on second pixel signals. A signal processor 112 outputs signals read out from the image pickup pixels after each charge accumulation operation of the image pickup pixels for a predetermined time period as the first pixel signals, and outputs signals obtained by plural charge accumulation operations of the focus detection pixels as the second pixel signals.
    Type: Grant
    Filed: October 2, 2009
    Date of Patent: May 21, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kazuyuki Nakagawa
  • Publication number: 20120120272
    Abstract: An image processing apparatus that can reduce the area where acquired images are held and reduce the load in image synthesis when successive images are to be generated. Acquired images are sequentially acquired and held in an acquired image storage circuit. A first set number of acquired images among the acquired images are synthesized to generate first composite images. The first composite images are held in a grouped image storage circuit. Second composite images from an image generated last to an image corresponding to a second set number among the first composite images are synthesized to generate a second composite image. The acquired images used to generate the first composite images are sequentially deleted.
    Type: Application
    Filed: November 7, 2011
    Publication date: May 17, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Kazuyuki Nakagawa
  • Publication number: 20120098126
    Abstract: The joint reliability in flip chip bonding of a semiconductor device is enhanced. Prior to flip chip bonding, flux 9 is applied to the solder bumps 5a for flip chip bonding over a substrate and reflow/cleaning is carried out and then flip chip bonding is carried out. This makes is possible to thin the oxide film over the surfaces of the solder bumps 5a and make the oxide film uniform. As a result, it is possible to suppress the production of local solder protrusions to reduce the production of solder bridges during flip chip bonding and enhance the joint reliability in the flip chip bonding of the semiconductor device.
    Type: Application
    Filed: October 14, 2011
    Publication date: April 26, 2012
    Inventors: Toshihiro IWASAKI, Takeumi KATO, Takanori OKITA, Yoshikazu SHIMOTE, Shinji BABA, Kazuyuki NAKAGAWA, Michitaka KIMURA
  • Patent number: 8147152
    Abstract: An image sensing apparatus comprises a shutter driving member which drives a shutter blade; a shutter spring which urges the shutter driving member; a shutter charge unit which charges the shutter spring, and is switched between an over-charged state and a travel prepared state; a driving unit which drives the shutter charge unit; a retaining unit which, when the shutter charge unit is set in the travel prepared state, retains the shutter driving member in a state in which the shutter spring is charged; a determination unit which determines whether or not the apparatus is executing a continuous shooting operation; and a controller which, when it is determined that the apparatus is executing the continuous shooting operation, controls to drive the shutter charge unit to the travel prepared state without stopping the shutter charge unit in the over-charged state after the charge operation of the shutter spring is complete.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: April 3, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kazuyuki Nakagawa
  • Patent number: 8106996
    Abstract: An image pickup apparatus includes a face detector configured to provide a face detection process based on image data obtained from an image pickup optical system that includes a focus lens configured to provide a focus control, a focus lens position extractor configured to extract a focus lens position at which the face detector has actually provided a successful face detection process from among focus lens positions set as a candidate position for the focus lens to be arranged when the face detector provides the face detection process, a focus control range setting part configured to set a focus control range in a focus range that contains the focus lens position extracted by the focus lens position extractor, and an autofocus controller configured to provide autofocus control in the focus control range set by the focus control range setting part.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: January 31, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kazuyuki Nakagawa