Abstract: A first thin film transistor including a gate electrode, a source region, a drain region, a GOLD region, and a channel region is formed at a first region at a TFT array substrate. A second thin film transistor including a gate electrode, a source region, drain region, a GOLD region, and a channel region is formed at a second region. The GOLD length (0.5 ?m) of the GOLD region of the second thin film transistor is set shorter than the GOLD length (1.5 ?m) of the GOLD region of the first thin film transistor. Accordingly, a semiconductor device directed to reducing the area occupied by semiconductor elements is obtained.

Abstract: A silicon nitride film and a silicon oxide film are formed on a glass substrate. On the silicon oxide film is formed a thin film transistor including a source region, a drain region, a channel region having a predetermined channel length, a GOLD region and an LDD region having an impurity concentration lower than the impurity concentration of the source region, a GOLD region and an LDD region having an impurity concentration lower than the impurity concentration of the drain region, a gate insulation film, and a gate electrode. The gate electrode is formed overlapping with and facing the channel region and the GOLD region. A semiconductor device is obtained, directed to improving source-drain breakdown voltage and AC stress resistance, and achieving desired current property.

Abstract: A silicon nitride film and a silicon oxide film are formed on a glass substrate. On the silicon oxide film is formed a thin film transistor T including a source region, a drain region, a channel region having a predetermined channel length, a first GOLD region having an impurity concentration lower than the impurity concentration of the source region, a second GOLD region having an impurity concentration lower than the impurity concentration of the drain region, a gate insulation film, and a gate electrode. The length of an overlapping portion in plane between the gate electrode and the second GOLD region in the direction of the channel length is set longer than the length in the direction of the channel region of an overlapping portion in plane between the gate electrode and the first GOLD region.

Abstract: A semiconductor device includes a glass substrate having a main surface, a polysilicon film formed on the main surface, having a channel region formed and having a source region and a drain region formed on opposing sides of the channel region, a gate insulating film provided so as to be in contact with the polysilicon film and containing oxygen, and a gate electrode provided in a position facing the channel region with the gate insulating film being interposed. The polysilicon film has a thickness larger than 50 nm and not larger than 150 nm. The polysilicon film contains hydrogen in a proportion not smaller than 0.5 atomic percent and not larger than 10 atomic percent. With such a structure, a semiconductor device attaining a large drain current and having a desired electric characteristic is provided.

Abstract: A vector of the present invention has DNA encoding a protein or a product having the same effect as the protein, the protein containing an amino acid sequence from amino acid numbers 47 to 802 in SEQ. ID. NO:2. Expression of the DNA gives human chondroitin synthase. By using human chondroitin synthase, it is possible to produce a saccharide chain having a repeating disaccharide unit of chondroitin. The DNA or part thereof may be used as a probe for hybridization for the human chondroitin synthase.

Abstract: A field-effect transistor including N?-extension regions, an N+-drain region, an N+-source region and a gate electrode at a surface of a silicon substrate. A sidewall insulating film on one of the side surfaces of the gate electrode partially covers the surface of the N?-extension region, and a sidewall insulating film on the other side surface entirely covers the N?-extension region. Further, a silicon oxide film covers the surface of N?-extension region not covered by the sidewall insulating film. Thereby, resistances of the gate electrode, source region, and drain region can be easily reduced in a transistor having extension regions, which are asymmetrical with respect to the gate electrode.

Abstract: A field-effect transistor including N−-extension regions, an N+-drain region, an N+-source region and a gate electrode is formed at a surface of a silicon substrate. A sidewall insulating film formed on one of the opposite side surfaces of the gate electrode partially covers the surface of the N−-extension region, and a sidewall insulating film formed on the side surface entirely covers the N−-extension region. Further, a silicon oxide film covers the surface of N−-extension region not covered with the sidewall insulating film. Thereby, resistances of the gate electrode, source region and drain region can be easily reduced in a transistor having extension regions, which are asymmetrical with respect to the gate electrode.

Abstract: In a miniaturized complete CMOS SRAM of a TFT load type, a field effect thin-film transistor (TFT) can achieve stable reading and writing operation of a memory cell and can reduce power consumption thereof. The field effect thin-film transistor formed on an insulator includes an active layer and a gate electrode. The gate electrode is formed on a channel region of the active layer with a gate insulating film therebetween. The active layer is formed of a channel region and source/drain regions. The channel region is formed of a monocrystal silicon layer and does not includes a grain boundary. The source/drain regions is formed of a polysilicon layer. The channel region has a density of crystal defects of less than 10.sup.9 pieces/cm.sup.2. The thin film transistor shows an ON current of 0.25 .mu.A/.mu.m per channel width of 1 .mu.m and an OFF current of 15 fA/.mu.m. The thin-film transistor can be applied to a p-channel MOS transistor serving as a load transistor in a memory cell of a CMOS type SRAM.

Abstract: Generation of new crystal defects in a monocrystalline semiconductor layer caused by heat treatment, oxidation treatment or polishing treatment is prevented in a method of manufacturing a semiconductor device of an SOI structure. Thus, unevenness in the properties of active devices formed on the monocrystalline semiconductor layers and their malfunctions can be restrained. A non-monocrystalline semiconductor layer formed on an insulator layer is melted to have a prescribed temperature distribution, and monocrystallized. The region of the obtained monocrystalline semiconductor layer corresponding to a high temperature portion in melting is selectively removed before the monocrystalline semiconductor layer is subjected to heat-treatment. Active devices are formed on the resultant island shaped monocrystalline semiconductor layers. The surface of the island shaped monocrystalline semiconductor layer may be polished to be planarized before the formation of the active device.

Abstract: In a miniaturized complete CMOS SRAM of a TFT load type, a field effect thin-film transistor (TFT) can achieve stable reading and writing operation of a memory cell and can reduce power consumption thereof. The field effect thin-film transistor formed on an insulator includes an active layer and a gate electrode. The gate electrode is formed on a channel region of the active layer with a gate insulating film therebetween. The active layer is formed of a channel region and source/drain regions. The channel region is formed of a monocrystal silicon layer and does not includes a grain boundary. The source/drain regions is formed of a polysilicon layer. The channel region has a density of crystal defects of less than 10.sup.9 pieces/cm.sup.2. The thin film transistor shows an ON current of 0.25 .mu.A/.mu.m per channel width of 1 .mu.m and an OFF current of 15 fA/.mu.m. The thin-film transistor can be applied to a p-channel MOS transistor serving as a load transistor in a memory cell of a CMOS type SRAM.

Abstract: In a method of manufacturing a stacked-type semiconductor device, firstly, a first semiconductor substrate having a first device formed thereon is covered with an interlayer insulating layer and a planarized polycrystalline silicon layer is formed on the interlayer insulating layer. The first semiconductor substrate and a second semiconductor substrate are joined together by putting the surface of the polycrystalline silicon layer in close contact with the surface of a refractory metal layer formed on the second semiconductor substrate, applying thermal treatment at 700.degree. C. or below and changing the refractory metal layer to silicide.

Abstract: A semiconductor device includes a capacitor, of which insulator has an improved durability. In the semiconductor device, a capacitor lower electrode 11 of the cylindrical capacitor includes a standing wall portion 11b, which is formed of a polysilicon layer having a large crystal grain diameter (1000 .ANG.-10000 .ANG.).

Abstract: A semiconductor device capable of effectively preventing a dielectric breakdown of a gate oxide film without adversely affecting the characteristics of a transistor and a process of manufacturing the same are disclosed. The semiconductor device comprises a SOI film 2 whose upper angular parts are rounded off by sputter etching and a gate oxide film 3 formed on SOI film 2 with an almost uniform thickness. Therefore, electric field concentration in the upper angular parts of SOI film 2 is reduced. Furthermore, the control characteristics of the transistor are enhanced by the uniform gate oxide film 3. As a result, a dielectric breakdown of the gate oxide film is effectively prevented without adversely affecting the characteristics of the transistor. Sputter etching enabling processing at a low temperature is used, so that the upper angular parts of SOI film 2 are rounded off without adversely affecting a semiconductor element formed in the lower layer.

Abstract: A semiconductor device includes a conductor layer (3, 7) having a silicon crystal, an insulator layer (5, 15) formed on the surface of the conductor layer (3, 7) having a contact hole therethrough to said surface of the conductor layer (3, 7), an interconnecting portion formed at a predetermined location in the insulator layer (5, 15) and having a contact hole (6, 9) the bottom surface of which becomes the surface of the conductor layer (3, 7), a barrier layer (14) formed at the bottom of said contact hole at least on the surface of the conductor layer (3, 7) in the interconnecting portion, and a metal silicide layer (12) formed on the barrier layer (14).

Abstract: A method of manufacturing a multi-layered semiconductor substrate comprising:a step of forming a first insulation film on the main surface of a semiconductor substrate composed of single crystals,a step of forming a first linear opening of a predetermined size reaching the semiconductor substrate at a predetermined position of the first insulation film,a step of forming second opening with the opening area of 25 .mu.m.sup.2 or less and reaching the semiconductor substrate along the first opening to the first insulation film at a position a spaced apart at least by 10 .mu.

Abstract: A semiconductor device capable of effectively preventing a dielectric breakdown of a gate oxide film without adversely affecting the characteristics of a transistor and a process of manufacturing the same are disclosed. The semiconductor device comprises a SOI film 2 whose upper angular parts are rounded off by sputter etching and a gate oxide film 3 formed on SOI film 2 with an almost uniform thickness. Therefore, electric field concentration in the upper angular parts of SOI film 2 is reduced. Furthermore, the control characteristics of the transistor are enhanced by the uniform gate oxide film 3. As a result, a dielectric breakdown of the gate oxide film is effectively prevented without adversely affecting the characteristics of the transistor. Sputter etching enabling processing at a low temperature is used, so that the upper angular parts of SOI film 2 are rounded off without adversely affecting a semiconductor element formed in the lower layer.

Abstract: Disclosed herein is a process for producing a single crystal layer of a semiconductor device, which comprises the steps of providing an oxide insulator layer separated by an opening part for seeding, on a major surface of a single crystal semiconductor substrate of the cubic system, providing a polycrystalline or amorphous semiconductor layer on the entire surface of the insulator layer inclusive of the opening part, then providing a protective layer comprising at least a reflective or anti-reflection film comprising stripes of a predetermined width, in a predetermined direction relative to the opening part and at a predetermined interval, the protective layer capable of controlling the temperature distributions in the semiconductor layer at the parts corresponding to the stripes or the parts not corresponding to the stripes, thereby completing a base for producing a semiconductor device, thereafter the surface of the base is irradiated with an energy beam through the striped reflective or anti-reflection fil

Abstract: In a method of manufacturing a stacked-type semiconductor device, firstly, a first semiconductor substrate having a first device formed thereon is covered with an interlayer insulating layer and a planarized polycrystalline silicon layer is formed on the interlayer insulating layer. The first semiconductor substrate and a second semiconductor substrate are joined together by putting the surface of the polycrystalline silicon layer in close contact with the surface of a refractory metal layer formed on the second semiconductor substrate, applying thermal treatment at 700.degree. C. or below and changing the refractory metal layer to silicide.

Abstract: A method of forming single-crystal semiconductor films, in which a single-crystal semiconductor substrate having a crystal axis transferred from a single-crystal semiconductor substrate is formed on an insulator layer via a seed hole which goes through the insulator layer which is formed on the single-crystal semiconductor substrate, comprises the steps of: forming a non-single-crystal semiconductor substrate connected to a single-crystal semiconductor substrate via a seed hole on an insulator layer; irradiating a compound beam which includes a first energy beam having a power density which is capable of melting a non-single-crystal semiconductor film and a second energy beam having a power density which is not capable of melting the non-single-crystal semiconductor film but capable of softening the insulator layer positioned below the non-single-crystal semiconductor film; and epitaxially growing the single-crystal semiconductor film in such a way that the non-single-crystal semiconductor film is melted and

Abstract: A semiconductor device includes a capacitor with an insulator having an improved durability. In the semiconductor device, a capacitor lower electrode 11 of the cylindrical capacitor includes a standing wall portion 11b which is formed of a polysilicon layer having a large crystal grain diameter (1000.ANG.-10000.ANG.).