Patents by Inventor Kazuyuki Sugahara

Kazuyuki Sugahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5214001
    Abstract: A manufacturing method of a semiconductor device having a planar single crystal semiconductor surface is disclosed. In the manufacturing method of a semiconductor device, an insulating film is formed on a semiconductor substrate, a noncrystal semiconductor film is formed on the insulating film, a stripe-like anti-reflection film is formed on the noncrystal semiconductor film, and laser beam is irradiated along the anti-reflection film. Because of the difference in temperature, a film with thicknesses different in a substrate region in which the anti-reflection film is formed and a region around it is formed. A film to be a machining allowance for polishing is formed on the single crystal semiconductor film, polishing is performed from the side of said film to be a machining allowance for polishing so that desired planar film thickness of the single crystal semiconductor film is implemented.
    Type: Grant
    Filed: January 14, 1991
    Date of Patent: May 25, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takashi Ipposhi, Kazuyuki Sugahara
  • Patent number: 5128732
    Abstract: A stacked semiconductor device has three-dimensional alternate layers of iconductor elements and insulating layers each electrically insulating the adjacent upper and lower layers of semiconductor elements, formed on a single crystal semiconductor substrate. A semiconductor is deposited in openings formed respectively in the insulating layers to form single crystal semiconductor layers each having the same crystal axis as the single crystal semiconductor substrate respectively over the insulating layers, and semiconductor elements are formed respectively in a plurality of layers. The opening formed through the upper insulating layer reaches the lower layer of the semiconductor element immediately below the same upper insulating layer, and is formed at a position spaced apart horizontally from the opening formed through the lower insulating layer immediately below the same upper insulating layer.
    Type: Grant
    Filed: May 27, 1988
    Date of Patent: July 7, 1992
    Assignee: Kozo Iizuka, Director General, Agency of Industrial Science & Technology
    Inventors: Kazuyuki Sugahara, Tadashi Nishimura, Shigeru Kusunoki, Yasuo Inoue, Yasuo Yamaguchi
  • Patent number: 5094714
    Abstract: A wafer structure for forming a semiconductor single crystal film comprises a semiconductor single crystal substrate, a plurality of recesses formed in a grooved shape to one main surface of the semiconductor single crystal substrate, insulation material embedded to the inside of these recesses, an insulation layer deposited over the insulation material and the semiconductor single crystal substrate and integrated with the insulation material and a polycrystalline or amorphous semiconductor layer to be recrystallized disposed over the insulation layer.A wafer structure with no or less grain boundaries can be obtained. Further, polycrystalline or amorphous semiconductor layer can be prevented from peeling off the substrate by the additional layering of a protecting insulation layer.
    Type: Grant
    Filed: October 31, 1990
    Date of Patent: March 10, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tadashi Nishimura, Kazuyuki Sugahara, Shigeru Kusunoki, Yasuo Inoue
  • Patent number: 5070030
    Abstract: Disclosed herein is a bipolar transistor and a method of manufacturing the same. The present invention provides a bipolar transistor in which a collector layer, a base layer and an emitter layer are transversely arranged in sequence through a monocrystal silicon layer formed on an insulation layer of a semiconductor substrate and a method of manufacturing the same. According to the present invention, parasitic capacity between a base and a collector can be reduced and p-n junction capacity between the collector and the substrate can be removed, thereby to achieve high-speed operation.
    Type: Grant
    Filed: October 31, 1990
    Date of Patent: December 3, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tatsuhiko Ikeda, Kazuyuki Sugahara, Shigeru Kusunoki, Kyusaku Nishioka
  • Patent number: 5006913
    Abstract: A field effect transistor is formed as a first semiconductor element on a main surface of a first semiconductor layer (1). An interlayer insulating film (10) constituted by a first insulating layer (101) and a second insulating layer (102) is formed on the first semiconductor element. The first insulating layer (101) is formed of a BPSG film having a glass transition point no higher than 750.degree. C. The second insulating layer (102) is formed of a silicon oxide film having a glass transition point higher than 750.degree. C. and a thickness no less than 2000 .ANG. and no more than 1 .mu.m formed on the first insulating layer (101). A second semiconductor layer (11) is formed on the second insulating layer (102) of the interlayer insulating film (10). The second semiconductor layer (11) is formed to be an island, with the peripheral portions isolated. A field effect transistor as a second semiconductor element is formed in the second semiconductor layer (11).
    Type: Grant
    Filed: November 2, 1989
    Date of Patent: April 9, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazuyuki Sugahara, Shigeru Kusunoki, Takashi Ipposhi
  • Patent number: 4990991
    Abstract: Disclosed herein is a bipolar transistor and a method of manufacturing the same. The present invention provides a biolar transistor in which a collector layer, a base layer and an emitter layer are transversely arranged in sequence through a monocrystal silicon layer formed on an insulation layer of a semiconductor substrate and a method of manufacturing the same. According to the present invention, parasitic capacity between a base and a collector can be reduced and p-n junction capacity between the collector and the substrate can be removed, thereby to achieve high-speed operation.
    Type: Grant
    Filed: October 30, 1987
    Date of Patent: February 5, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tatsuhiko Ikeda, Kazuyuki Sugahara, Shigeru Kusunoki, Kyusaku Nishioka
  • Patent number: 4953125
    Abstract: A semiconductor memory device includes a first trench serving as a memory cell formed in a p type semiconductor substrate, a first n type semiconductor region formed adjacent to the trench region and on the major surface of the semiconductor substrate, a conductive layer serving as an electron active region formed adjacent to the first n type region and on the major surface of the semiconductor substrate, a second n type semiconductor region formed adjacent to the electron active region and on the major surface of the semiconductor substrate, a second trench formed adjacent to the second n type semiconductor region in the major surface of the semiconductor substrate which is shallower than the first trench, an interconnection layer serving as a bit line formed in a self-aligning manner in the sidewall portion of the second trench which is shallower than the first trench and a gate electrode serving as a word line formed in the upper portion of the conductive layer through an oxide film.
    Type: Grant
    Filed: March 25, 1988
    Date of Patent: August 28, 1990
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshinori Okumura, Akihiko Ohsaki, Kazuyuki Sugahara, Tatsuhiko Ikeda
  • Patent number: 4870031
    Abstract: In a method of manufacturing a semiconductor device comprising melting an amorphous or polycrystalline first semiconductor layer formed on the surface of a first dielectric layer by irradiating energy rays thereon, and converting the same into single crystals by the subsequent lowering of the temperature and forming a second dielectric layer and a second semiconductor layer on the first semiconductor layer. Energy rays are irradiated under the condition capable of melting the first semiconductor layer through the second semiconductor layer and the second dielectric layer and, after the completion of the conversion into single crystals, the second semiconductor layer and the second dielectric layer are eliminated through etching.
    Type: Grant
    Filed: September 30, 1987
    Date of Patent: September 26, 1989
    Assignee: Kozo Iizuka, Director General, Agency of Industrial Science and Technology
    Inventors: Kazuyuki Sugahara, Tadashi Nishimura, Shigeru Kusunoki, Yasuo Inoue
  • Patent number: 4861418
    Abstract: A method of manufacturing a semiconductor crystalline layer comprising the following steps: a step of forming, on a single crystalline substrate composed of a semiconductor having a main face on <001> face and having a diamond-type crystal structure, an orientation flat face in which the direction of the intersection with the main face makes a predetermined angle relative to the direction <110> on the main face and which serves as a reference for defining the direction of arranging semiconductor chips formed on the substrate; a step of forming, on the main face of the substrate, an insulation layer at least a portion of which has an opening reaching the main face and which insulates the substrate at the region other than the opening; a step of forming a semiconductor layer composed of a polycrystalline or amorphous semiconductor on the surface of the opening and the insulation layer; a step of forming a reflectivity varying layer which is in the direction in parallel with or vertical to the inters
    Type: Grant
    Filed: March 6, 1987
    Date of Patent: August 29, 1989
    Assignee: Kozo Iizuka, Director General, Agency of Industrial Science and Technology
    Inventors: Tadashi Nishimura, Yasuo Inoue, Kazuyuki Sugahara, Shigeru Kusunoki
  • Patent number: 4845537
    Abstract: A vertical MOS transistor having its channel length determined by the thickness of an insulating layer provided over a semiconductor substrate, rather than by the depth of a trench in which the transistor is formed. As a result, the characteristics of the transistor as relatively unaffected by doping and heat-treatment steps which are performed during formation. Also, the transistor may be formed so as to occupy very little surface area, making it suitable for application in high-density DRAMs.
    Type: Grant
    Filed: December 1, 1987
    Date of Patent: July 4, 1989
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tadashi Nishimura, Kazuyuki Sugahara, Shigeru Kusunoki, Akihiko Ohsaki
  • Patent number: 4822752
    Abstract: Disclosed herein is a process for producing a single crystal layer of a semiconductor device, which comprises the steps of providing an oxide insulator layer separated by an opening part for seeding, on a major surface of a single crystal semiconductor substrate of the cubic system, providing a polycrystalline or amorphous semiconductor layer on the entire surface of the insulator layer inclusive of the opening part, then providing a protective layer comprising at least a reflective or anti-reflection film comprising strips of a predetermined width, in a predetermined direction relative to the opening part and at a predetermined interval, the protective layer capable of controlling the temperature distributions in the semiconductor layer at the parts corresponding to the stripes or the parts not corresponding to the stripes, thereby completing a base for producing a semiconductor device, thereafter the surface of the base is irradiated with an energy beam through the striped reflective or anti-reflection film
    Type: Grant
    Filed: March 6, 1987
    Date of Patent: April 18, 1989
    Assignee: Agency of Industrial Science and Technology
    Inventors: Kazuyuki Sugahara, Tadashi Nishimura, Shigeru Kusunoki, Yasuo Inoue
  • Patent number: 4801548
    Abstract: A Petri dish for cultivating bacteria used for isolating the bacteria in an enrichment culture for performing drug susceptibility tests, etc. having a mouth covered with at least one sheet and at least one small opening provided on the bottom of the Petri dish, partitions having a height equal to the distance between the bottom of the Petri dish and the sheet may be provided in the Petri dish, and a sealing lid may be fitted over the small openings. A method of inspecting drug susceptibility of bacteria which are isolated from clinical specimens etc. or purely cultured after their isolation using the Petri dish. The method using the fractionized Petri dish having a pervious sheet as the cultivation surface assorts different kinds of media from each other, the media being different in the kind of drug contained in each media or media containing the same drug but in different concentrations in each section of the Petri dish into which the bacteria is inoculated.
    Type: Grant
    Filed: November 20, 1987
    Date of Patent: January 31, 1989
    Assignee: Kobayashi Pharmaceutical Co., Ltd.
    Inventors: Tetsuya Takakura, Kenzi Asano, Kazuyuki Sugahara
  • Patent number: 4787740
    Abstract: An apparatus for determining crystal orientation comprises: a polarizer for polarizing an incident light beam; a polarization analyzer for selecting light having a selected polarization direction in Raman scattered light; and a synchronizer for enabling synchronous rotations of the polarizer and the polarization analyzer.
    Type: Grant
    Filed: February 5, 1987
    Date of Patent: November 29, 1988
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuo Inoue, Tadashi Nishimura, Kazuyuki Sugahara, Shigeru Kusunoki
  • Patent number: 4778269
    Abstract: In a method for determining orientation of a crystal with polarization selective Raman microprobe spectroscopy, polarization angles of both light incident on the crystal and Raman scattered light emitted from the crystal are varied coincidently in ordinary circumstances and only either one of the polarization angles is varied in only case that intensity of the scattered beam does not change substantially in spite of the coincident variation of both the polarization angles.
    Type: Grant
    Filed: February 6, 1987
    Date of Patent: October 18, 1988
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuo Inoue, Tadashi Nishimura, Kazuyuki Sugahara, Shigeru Kusunoki
  • Patent number: 4775628
    Abstract: A Petri dish for cultivating bacteria used for isolating the bacteria in an enrichment culture for performing drug susceptibility tests, etc. having a mouth covered with at least one sheet and at least one small opening provided on the bottom of the Petri dish, partitions having a height equal to the distance between the bottom of the Petri dish and the sheet may be provided in the Petri dish, and a sealing lid may be fitted over the small openings. A method of inspecting drug susceptibility of bacteria which are isolated from clinical specimens etc. or purely cultured after their isolation using the Petri dish. The method using the fractionized Petri dish having a pervious sheet as the cultivation surface assorts different kinds of media from each other, the media being different in the kind of drug contained in each media or media containing the same drug but in different concentrations in each section of the Petri dish into which the bacteria is inoculated.
    Type: Grant
    Filed: September 11, 1985
    Date of Patent: October 4, 1988
    Assignee: Kobayashi Pharmaceutical Co., Ltd.
    Inventors: Tetsuya Takakura, Kenzi Asano, Kazuyuki Sugahara
  • Patent number: 4714684
    Abstract: In a method of manufacturing a semiconductor device of a three-dimensional structure having a semiconductor substrate and another single crystal semiconductor layer formed thereon, the another single crystal semiconductor layer is prepared by melting a vapor-deposited amorphous or polycrystalline semiconductor layer by the energy of laser beams then solidifying and converting the layer into single crystals. For initiating the melting at selected regions of the layer, the layer is formed at the surface thereof with a silicon nitride film of a uniform thickness and a silicon nitride film with a thickness at the region corresponding to the selected region different from that of the remaining region. The region thicker or thinner than other region reflects the laser energy at different reflectivity thereby to provide a desired temperature distribution.
    Type: Grant
    Filed: March 26, 1986
    Date of Patent: December 22, 1987
    Assignee: Agency of Industrial Science and Technology
    Inventors: Kazuyuki Sugahara, Tadashi Nishimura, Shigeru Kusunoki, Yasuo Inoue
  • Patent number: 4694143
    Abstract: A zone melting apparatus, in accordance with the present invention for monocrystallizing a semiconductor layer in a layered substance, includes: an upper elongated heater for zone melting of the semiconductor layer, the upper heater being disposed above and parallel to the semiconductor layer; a plurality of lower elongated heaters for heating the whole layered substance, the lower heaters being disposed in a plane below and parallel to the layered substance and the axis of each of the lower heaters being substantially perpendicular to the axis of the upper heater; a plurality of power suppliers for supplying electric power to the lower heaters; one or more temperature sensors for estimating the temperature of the layered substance; and a controller for controlling the power suppliers in response to the output of the temperature sensor(s), the controller making control so that the temperature of the central portion of the layered substance is slightly lower than that of the outer portions thereof.
    Type: Grant
    Filed: December 31, 1985
    Date of Patent: September 15, 1987
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tadashi Nishimura, Kazuyuki Sugahara, Shigeru Kusunoki, Yasuo Inoue
  • Patent number: 4661167
    Abstract: A method for manufacturing a semiconductor device, which comprises: a first process for producing a semiconductor layer of polycrystalline silicon or amorphous silicon on the surface of a substrate of insulator or a substrate made up by forming an insulating layer on a basic semiconductor; a second process for producing an island of semiconductor layer surrounded by dielectric materials from the semiconductor layer; a third process for producing a film of Si.sub.3 N.sub.4 on the island of semiconductor layer, or on a film of SiO.sub.2 formed on the island; a fourth process for removing the film of Si.sub.3 N.sub.4 at a predetermined region on the island; and a fifth process for irradiating with scanning an energy beam to the island of semiconductor layer so as to melt and recrystallize the island, thereby monocrystallizing or increasing the size of crystal grains at at least a partial region thereof.
    Type: Grant
    Filed: December 3, 1984
    Date of Patent: April 28, 1987
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shigeru Kusunoki, Tadashi Nishimura, Kazuyuki Sugahara