Abstract: A circuit board includes an input side and an output side oppositely arranged, and the output side is configured to electrically connect to a display substrate. The circuit board includes a plurality of signal lines extending in a direction from the input side to the output side. Each of the plurality of signal lines includes a main body and a plurality of output branches. Each of the plurality of output branches is connected to one end of the main body close to the output side and has a same line width. A line width of the main body is greater than a sum of line widths of all the output branches belonging to same signal line.

Abstract: Provided are a display substrate and a display device. The first display region includes at least two domains spaced apart in the first direction and a first space between the at least two domains, the second display region includes at least two domains spaced apart in the first direction and a second space located between the at least two domains of the second display region; each pixel units further includes a discharge line and a common electrode strip, the discharge line includes a first conductive part and a second conductive part, the first conductive part is at the first space, the second conductive part is at the second space, the common electrode strip is at an edge of the first display region adjacent to the data lines, and no common electrode strip is arranged on an edge of the second display region adjacent to the data lines.

Abstract: A transformer structure can include: a substrate encapsulating at least two windings that are isolated from each other, where each winding includes a coil body and lead-out terminals coupled to the coil body; and a magnetic encapsulation body encapsulating at least one side of the substrate, where the magnetic encapsulation body includes an insulating main material and magnetic particles dispersed in the insulating main material.

Abstract: The present disclosure provides an array substrate and a manufacturing method thereof, and a display apparatus. The array substrate includes a plurality of gate lines (20) and a plurality of data lines (50) disposed on a base substrate (11), the plurality of gate lines (20) extend along a first direction, the plurality of data lines (50) extend in a second direction, the plurality of gate lines (20) and the plurality of data lines (50) are intersected to define a plurality of sub-pixels, the sub-pixel includes a thin film transistor (10), a pixel electrode (80) and a common electrode (90), the common electrode (90) in one sub-pixel is connected with the common electrode (90) in the adjacent sub-pixel through a common connection portion (110).

Abstract: A display panel, including: a substrate including a display region and a non-display region; a second conductive layer including more than one gate line located in the display region, and more than one virtual gate line located in the non-display region; a virtual conductive part, located in the non-display region, where the virtual conductive part is located in a different conductive layer from the virtual gate line, an orthographic projection of the virtual conductive part on the substrate is located within an orthographic projection of the virtual gate line on the substrate, and the virtual conductive part is configured to form an equivalent capacitance with the virtual gate line; and a RC load of the virtual gate line matches with a RC load of the gate line.

Abstract: Provided is an array substrate. The array substrate includes: a base substrate; a plurality of clock lines; a plurality of clock leads; a plurality of shift register units; and a compensation capacitor plate, disposed on the base substrate and in the peripheral region, wherein the compensation capacitor plate is connected to the clock lead, and the compensation capacitor plate and the clock lead are in different layers, an area of the compensation capacitor plate being negatively correlated with a length of the clock lead connected to the compensation capacitor plate.

Abstract: A thin film transistor, an array substrate and a display device are provided. The thin film transistor is on a base substrate and includes a gate electrode, a first electrode, and a second electrode on the base substrate. The gate electrode includes a first body portion and a first extension portion extending along the first direction, electrically connected with the first body portion, and spaced apart from the first body portion by a first spacing.

Abstract: A driving module includes N driving circuits connected in series; the driving circuit includes an input terminal; N is a positive integer; input terminals of first a stages of driving circuits included in the driving module are electrically connected to an initial voltage line; a is a positive integer; an input terminal of an nth stage of driving circuit included in the driving module is electrically connected to an output terminal of an (n?m)th stage of driving circuit included in the driving module through an input cascade line; n and m are positive integers, and m is less than n; the driving module further includes at least one connection line, there is an overlapping portion between an orthographic projection of the connection line on the base substrate and an orthographic projection of the initial voltage line on the base substrate.

Abstract: An Embodiment of the present disclosure provide a display substrate, including a base substrate, and a plurality of first scanning lines, a plurality of second scanning lines, a plurality of data lines, a plurality of common electrodes and a plurality of pixel electrodes on the base substrate. The second scanning lines are parallel to the data lines, and the second scanning lines, the common electrodes and the pixel electrodes are in different layers. The common electrodes are located on a side of the second scanning lines and the data lines away from the base substrate, and on a side of the pixel electrodes proximal to the base substrate. An orthographic projection of one of the data line and the second scanning line on the base substrate is located in a spacer region between adjacent pixel electrodes.

Abstract: The present disclosure provides a display device. The display device includes: a liquid crystal display panel; a liquid crystal light control panel located on the light incident side of the liquid crystal display panel; and at least two haze layers located on the light emitting side of the liquid crystal display panel.

Abstract: A laminated transformer can include: a plurality of magnetic layers; a plurality of coil layers including a primary coil having a first type of coil layer, and a secondary coil having a second type of coil layer, where each coil layer is laminated between a pair of the plurality of magnetic layers; and a plurality of non-magnetic layers, where a first of the plurality of non-magnetic layers is disposed between an adjacent pair of the coil layers in order to increase a coupling coefficient between the primary and secondary coils.

Abstract: A display panel includes: a first active area and at least one second active area, a substrate; a plurality of sub-pixels located on the substrate, the plurality of sub-pixels being in the first active area, and each of the sub-pixels including a common electrode; grid lines and data lines, at least one of the data lines being located at a junction of the first active area and the second active area; a plurality of first conductive patterns at least in the second active area, and the first conductive patterns being electrically connected to one of the grid lines or the common electrode; and a plurality of second conductive patterns in the second active area and electrically connected to the data line at the junction, orthographic projections of part first conductive patterns on the substrate overlap orthographic projections of the second conductive patterns on the substrate.

Abstract: An array substrate includes a base substrate, pixel electrodes and common electrodes, first scan lines, second scan lines and data lines. The pixel electrode has first electrode strips disposed at intervals in a row direction. The common electrodes and the pixel electrodes are disposed on the same layer, and the common electrodes have second electrode strips disposed at intervals. The second electrode strips and the first electrode strips are alternatively arranged. The first scan line is located between two adjacent rows of pixel electrodes. The second scan line is located between two adjacent columns of pixel electrodes and is electrically connected to the first scan line, and the second scan line has a scan signal input terminal. The data line has a data signal input terminal. An orthographic projection of the data line on the base substrate intersects with a central region of the pixel electrode on the base substrate.

Abstract: A method for driving a display panel and a display device, the method includes: acquiring an original grayscale value of each sub-pixel in an mth row and a target grayscale value corresponding to a data voltage input to each sub-pixel in an (m?1)th row m being an integer greater than 1; if, in a same column, the original grayscale value of the sub-pixel in the mth row is larger than the target grayscale value corresponding to the data voltage input to the sub-pixel in the (m?1)th row, determining a target grayscale value of each sub-pixel in the mth row according to the original grayscale value of the sub-pixel in the mth row and the target grayscale value of the sub-pixel in the (m?1)th row inputting a data voltage to a data line in the display panel according to the target grayscale value of each sub-pixel in the mth row.

Abstract: The present disclosure provides a display device. The display device includes: a liquid crystal display panel; a liquid crystal light control panel located on the light incident side of the liquid crystal display panel; and at least two haze layers located on the light emitting side of the liquid crystal display panel.

Abstract: A driving method of a display panel and a display apparatus provided by embodiments of the present disclosure include: when a display mode switching startup instruction is received, a non-counting state is entered. The display panel is driven to display a first set picture, and a current display mode is switched to a target display mode. When a data mode switching completing instruction is received, a counting state is entered.

Abstract: Charging and power supply optimization method and apparatus for a charging management system are provided. The method includes: obtaining information about power supply, transformation and distribution of a charging station, capability information of a charging facility, output information of a charging terminal, and charging demand information of an electric vehicle, determining a charging capability, power supply capability and an actual charging capacity of a charging facility system at the charging station, obtaining a model output result based on a pre-trained deep learning time series prediction algorithm model, generating a charging power allocation instruction in combination with an actual charging capacity of a charging facility system at the charging station, and a charging demand of a to-be-charged electric vehicle, and distributing electric energy to each charging facility.

Abstract: A laminated transformer can include: a plurality of magnetic layers; a plurality of coil layers including a primary coil having a first type of coil layer, and a secondary coil having a second type of coil layer, where each coil layer is laminated between a pair of the plurality of magnetic layers; and a plurality of non-magnetic layers, where a first of the plurality of non-magnetic layers is disposed between an adjacent pair of the coil layers in order to increase a coupling coefficient between the primary and secondary coils.