Abstract: A common voltage calibration circuit and a driving method thereof, a circuit board and a display device are provided. The common voltage calibration circuit includes a difference circuit, a compensation circuit and a summing circuit; the difference circuit is configured to perform a difference processing on a common voltage provided by the common voltage input terminal and a feedback common voltage provided by the common voltage feedback terminal to output a difference value signal; the compensation circuit is configured to receive the difference value signal and compensate the common voltage based on the difference value signal; and the summing circuit is configured to superimpose at least two compensation signals output by the compensation circuit and output through the common voltage output terminal.

Abstract: The present disclosure provides an array substrate, a dimming liquid crystal panel and a display panel. The array substrate includes: a first transparent electrode layer with a plurality of slit structures, wherein the first transparent electrode layer includes a plurality of domains with an equal area, the plurality of domains include at least two types of domains, the at least two types of domains are arranged in a mosaic shape; a plurality of gate lines extending along a row direction and a plurality of data lines extending along a column direction, the plurality of gate lines and the plurality of data lines crossing to define a plurality of dimming regions arranged in an array.

Abstract: The present disclosure provides a driving method of a display device and a display device. The driving method of the display device includes: inputting a gate signal with a length of a first duration to each of gate lines; and inputting a data signal to each of data lines to drive the display device for displaying. Among M data lines crossing the gate line in a direction of the gate line from a signal input terminal to an terminal away from the signal input terminal, a start time at which an mth data line input with the data signal is delayed by a second duration, relative to the start time at which a first data line closest to the signal input terminal of the gate line is input with the data signal, and the second duration is less than the first duration.

Abstract: A voltage control circuit comprises a sampling sub-circuit and a control sub-circuit. The sampling sub-circuit is configured to detect a potential difference between an output voltage and an input voltage to obtain a first voltage and output the first voltage to the control sub-circuit. The control sub-circuit is configured to compare a magnitude of the first voltage with a first voltage threshold, if the first voltage is less than the first voltage threshold, output the input voltage as the output voltage, and, if the first voltage is greater than or equal to the first voltage threshold, superimpose and output the input voltage and a bootstrap voltage as the output voltage.

Abstract: A package assembly can include: a die electrically connected to outer pins of the package assembly; an electronic component located above the die and electrically connected to the die, wherein the electronic component is connected to the outer pins of the package assembly through conductive pillars; and a heat dissipation structure located between the die and the electronic component to facilitate heat dissipation of the electronic component, where the heat dissipation structure physically isolates the die and the electronic component such that electromagnetic interference from the electronic component to the die is substantially prevented.

Abstract: Provided are a pixel circuit, a display panel, a display device and a pixel driving method, the pixel circuit including: a data compensation circuit, a storage circuit, a driving transistor and a replication transistor, the replication transistor and the driving transistor have the same structure; the data compensation circuit writes, in an initialization stage, a first voltage into a first node under a control of a second control signal and a third control signal; and to write, in a data writing and compensation stage, under a control of the third control signal and a first control signal, a data voltage to a first electrode of the replication transistor to detect a threshold voltage thereof, write a compensation voltage to the first node for storage by the storage circuit, the compensation voltage being equal to a sum of the data voltage and the threshold voltage of the replication transistor.

Abstract: A pixel driving circuit, a pixel driving method, an array substrate and a display device are provided. The pixel driving circuit includes a plurality of pixel regions; a pixel electrode array; and a thin film transistor switch, where at least one thin film transistor switch is arranged in each pixel region; the polarities of input voltage signals to two adjacent pixel electrodes are opposite in a same row of pixel electrodes; M rows of pixel electrodes are divided into Q pixel groups, including a first pixel group, a second pixel group and (Q?2) third pixel groups located between the first pixel group and the second pixel group, and each third pixel group includes at least q rows of pixel electrodes; and in the same column of pixel electrodes, the polarities of input voltage signals to the pixel electrodes in the same pixel group are the same, and the polarities of input voltage signals to the pixel electrodes of two adjacent pixel groups are opposite.

Abstract: Some embodiments of the present disclosure provide a shift register unit, a gate driver, a driving method thereof and a display device. The shift register unit includes: an output circuit, configured to receive a clock signal and output the clock signal to an output signal terminal under control of a voltage of a pull-up control node; a pull-down control circuit, configured to receive a control voltage signal and control the voltage of the pull-up control node and a voltage of the output signal terminal according to the control voltage signal; and an output control circuit, configured to receive a first voltage signal and the control voltage signal, and control the voltage of the output signal terminal in response to the first voltage signal and the control voltage signal.

Abstract: A display driving method includes: determining, by a timing controller, an actual grayscale value of a sub-pixel image in an X-th row and a Y-th column according to a preset grayscale value of a sub-pixel image in an (X?1)-th row and the Y-th column and a preset grayscale value of the sub-pixel image in the X-th row and the Y-th column of an image frame to be displayed. The image frame to be displayed includes J rows and Q columns of sub-pixel images. X is greater than or equal to 2, and is less than or equal to J. Y is greater than or equal to 1, and is less than or equal to Q, and X, Y, J, and Q are all integers.

Abstract: A display panel having a display area and a peripheral area is provided. The display panel includes a first display substrate; a second display substrate facing the first display substrate; a sealant layer in the peripheral area and between the first display substrate and the second display substrate, configured to seal the first display substrate and the second display substrate together to form a cell; and an elastic support layer in the peripheral area and between the first display substrate and the second display substrate. The elastic support layer encircled by the sealant layer and spaced apart from the sealant layer. The elastic support layer substantially surrounds the display area. The elastic support layer is configured to be in direct contact with the first display substrate and in direct contact with the second display substrate.

Abstract: A thin film transistor, an array substrate and a display device. The thin film transistor includes a gate electrode, a first electrode, and a second electrode on the base substrate. The gate electrode includes a first body portion and a first extension portion extending along the first direction, electrically connected with the first body portion, and spaced apart from the first body portion by a first spacing. The first electrode includes a first overlapping end, an orthographic projection of the first overlapping end on the base substrate at least partially overlaps with an orthographic projection of the first body portion on the base substrate; a first compensation end at a side of the first overlapping end away from the first body portion; and a first intermediate portion connecting the first overlapping end and the first compensation end.

Abstract: The present disclosure provides a gate driving circuit, a control method thereof, and a display device. The gate driving circuit includes: an input sub-circuit (110) configured to convert the potential of a first node (N1) from a first level to a second level; an output sub-circuit (120) configured to output a gate driving signal (SOUT); a first reset sub-circuit (130) configured to reset the potential of the first node (N1); at least one noise reduction sub-circuit (140) configured to maintain the potentials of the first node (N1) and an output end of the output sub-circuit (120) at the first level in the case that the potential of the first ode (N1) is reset; and a function maintaining sub-circuit (150) configured to control the noise reduction sub-circuit (140) to operate so that the noise reduction sub-circuit (140) interrupts the first node (N1) and a first voltage terminal.

Abstract: An array substrate and a method for producing the same are disclosed. The array substrate includes a metal pattern and an electrically conductive pattern sequentially formed on a base substrate, the electrically conductive pattern being insulated from the metal pattern. The array substrate further includes a static charge releasing pattern formed in a same layer and made of a same material as the electrically conductive pattern, and which is insulated from the electrically conductive pattern. The metal pattern is a signal line running through a display area of the array substrate, and includes an input end, an output end, and a body portion between the input end and the output end. The output end of the signal line includes an island-like structure, and a width of the island-like structure is greater than that of the body portion. The static charge releasing pattern is electrically connected with the island-like structure.

Abstract: According to a liquid crystal display panel and a display device in the present disclosure, since at least one of a first polarizer and a second polarizer has a light scattering structure, polarized light of corresponding colors transmitted by sub-pixel units with different colors in a liquid crystal display structure can be uniformly diffused by the light scattering structure. That is to say, the light scattering structure plays a role for uniformly mixing the polarized light of different colors. Therefore, the rainbow pattern phenomenon is effectively improved or even eliminated, and the display quality is improved.

Abstract: The present application provides an apparatus for a photo-alignment process. The apparatus for a photo-alignment process includes a reflector, an up-conversion layer, and a polarizer optically coupled together. The reflector is configured to reflect an infrared light and provide a reflected infrared light to the up-conversion layer. The up-conversion layer is configured to convert the reflected infrared light to an ultraviolet light, and provide the ultraviolet light to the polarizer. The polarizer is configured to convert the ultraviolet light to a polarized ultraviolet light for the photo-alignment process.

Abstract: An array substrate having a display area, a peripheral area, and a bonding area inside the peripheral area is provided. The array substrate includes a bonding pad in the bonding area, the bonding pad configured to be connected to a peripheral circuit through a bonding connector, a test signal line including a first portion and a second portion. The first portion is in the peripheral area and substantially surrounds the display area. The first portion is electrically connected to the bonding pad. The first portion is completely inside the array substrate and has no exposed terminal. The second portion is in the bonding area. A first terminal of the second portion is electrically connected to the bonding pad. A second terminal of the second portion has an end along an edge of the array substrate in the bonding area.

Abstract: The disclosure relates to a display substrate. The display substrate may include a semiconductor pattern and a first conductive pattern stacked on a base substrate, and a second conductive pattern electrically connected to the first conductive pattern. A first orthographic projection of the first conductive pattern on the base substrate may fall within a second orthographic projection of the semiconductor pattern on the base substrate, and a distance between the second orthographic projection and a fourth orthographic projection of a display electrode of the display substrate on the base substrate ma be greater than a distance between a third orthographic projection of the second conductive pattern on the base substrate and the fourth orthographic projection.

Abstract: The present disclosure relates to the field of display technology, and provides a display module and a display device. The display module includes a first display sub-panel, where the first display sub-panel includes: a first display sub-panel including a plurality of first pixel units; and a second display sub-panel arranged at a light-entering side of the first display sub-panel and including a plurality of second pixel units. Each second pixel unit corresponds to at least one first pixel unit, an orthogonal projection of each second pixel unit onto the first display sub-panel coincides with the corresponding first pixel unit, and the second display sub-panel is a vertical-electric-field-type liquid crystal display panel.

Abstract: An aging device for a display panel includes: a bearing device, including a bearing surface that is configured to bear the display panel; a fixture, including a plurality of pins which are configured to provide a screen turning-on signal for the display panel; a first electrode and a second electrode, wherein the first electrode and the second electrode are in an opposite arrangement and configured to apply an electric field to the display panel. The aging device achieves aging by providing an electric field for the display panel, avoids the burning of the thin film transistor devices of the display panel caused by the excessive bias and allows the thin film transistors at different positions to be uniformly aged, and is also easy to operate and implement.

Abstract: Provided are a shift register and a driving method thereof, a gate driving circuit, and a display apparatus. The shift register is disposed on a display panel. An operating process of the display panel includes a start-up phase and a display phase. The shift register includes a shift register unit, a start-up discharge circuit, a first control end, a second control end, a signal output end and a first power supply end; the shift register unit is configured to output a gate driving signal to the signal output end in the display phase; the start-up discharge circuit is configured to provide a signal of the first power supply end to the signal output end under control of the first control end and the second control end in the start-up phase.