Patents by Inventor Kedarnath Balakrishnan

Kedarnath Balakrishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220122652
    Abstract: A memory controller interfaces with a random access memory over a memory channel. A refresh control circuit monitors an activate counter which counts a rolling number of activate commands sent over the memory channel to a memory region of the memory. In response to the activate counter being above an intermediate management threshold value, the refresh control circuit only issue a refresh management (RFM) command if there is no REF command currently held at the refresh command circuit for the memory region.
    Type: Application
    Filed: December 29, 2021
    Publication date: April 21, 2022
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Kevin M. Brandl, Kedarnath Balakrishnan, Jing Wang, Guanhao Shen
  • Publication number: 20220091921
    Abstract: A data processor includes provides memory commands to a memory channel according to predetermined criteria. The data processor includes a first error code generation circuit, a second error code generation circuit, and a queue. The first error code generation circuit generates a first type of error code in response to data of a write request. The second error code generation circuit generates a second type of error code for the write request, the second type of error code different from the first type of error code. The queue is coupled to the first error code generation circuit and to the second error code generation circuit, for provides write commands to an interface, the write commands including the data, the first type of error code, and the second type of error code.
    Type: Application
    Filed: December 7, 2021
    Publication date: March 24, 2022
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Kedarnath Balakrishnan, James R. Magro, Kevin Michael Lepak, Vilas Sridharan
  • Publication number: 20220058141
    Abstract: A memory controller includes a memory channel controller that uses multiple groups of command queue and arbiter pairs. Each arbiter is coupled to a respective command queue to select memory access commands from each command queue according to predetermined criteria. Each arbiter selects from among the memory access requests in each command queue independently based on the predetermined criteria and sends selected memory access requests to a selector that serves as a second level arbiter which sends the request to a memory subchannel.
    Type: Application
    Filed: October 30, 2020
    Publication date: February 24, 2022
    Inventors: James R. Magro, Kedarnath Balakrishnan, Brendan T. Mangan
  • Publication number: 20220028450
    Abstract: A method for performing stutter of dynamic random access memory (DRAM) where a system on a chip (SOC) initiates bursts of requests to the DRAM to fill buffers to allow the DRAM to self-refresh is disclosed. The method includes issuing, by a system management unit (SMU), a ForceZQCal command to the memory controller to initiate the stutter procedure in response to receiving a timeout request, such as an SMU ZQCal timeout request, periodically issuing a power platform threshold (PPT) request, by the SMU, to the memory controller, and sending a ForceZQCal command prior to a PPT request to ensure re-training occurs after ZQ Calibration. The ForceZQCal command issued prior to PPT request may reduce the latency of the stutter. The method may further include issuing a ForceZQCal command prior to each periodic re-training.
    Type: Application
    Filed: July 24, 2020
    Publication date: January 27, 2022
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Jing Wang, Kedarnath Balakrishnan, Kevin M. Brandl, James R. Magro
  • Patent number: 11222685
    Abstract: A memory controller interfaces with a dynamic random access memory (DRAM) over a memory channel. A refresh control circuit monitors an activate counter which counts a rolling number of activate commands sent over the memory channel to a memory region of the DRAM. In response to the activate counter being above an intermediate management threshold value, the refresh control circuit only issue a refresh management (RFM) command if there is no REF command currently held at the refresh command circuit for the memory region.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: January 11, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kevin M. Brandl, Kedarnath Balakrishnan, Jing Wang, Guanhao Shen
  • Patent number: 11200106
    Abstract: A data processing system includes a memory channel, a memory coupled to the memory channel, and a data processor. The data processor is coupled to the memory channel and accesses the memory over the memory channel using a packet structure defining a plurality of commands and having corresponding address bits, data bits, and user bits. The data processor communicates with the memory over the memory channel using a first type of error code. In response to a write access request, the data processor calculates a different, second type of error code and appends each bit of the second type of error code as a corresponding one of the user bits. The memory stores the user bits in the memory in response to a write command, and transfers the user bits to the data processor in a read response packet in response to a read command.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: December 14, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kedarnath Balakrishnan, James R. Magro, Kevin Michael Lepak, Vilas Sridharan
  • Publication number: 20210382661
    Abstract: A memory controller selects from among a plurality of memory access commands including volatile memory reads, volatile memory writes, non-volatile memory reads, and non-volatile memory writes. The selected memory access commands are transmitted to a heterogenous memory channel coupled to a non-volatile memory and a volatile memory. The non-volatile read commands that are transmitted are stored in a non-volatile command queue (NV queue). A ready response is received from the non-volatile memory indicating that responsive data is available for an associated one of the non-volatile read commands. In response to receiving the ready response, a send command is transmitted for commanding the non-volatile memory to send the responsive data.
    Type: Application
    Filed: August 23, 2021
    Publication date: December 9, 2021
    Applicant: Advanced Micro Devices, Inc.
    Inventors: James R. Magro, Kedarnath Balakrishnan
  • Patent number: 11194382
    Abstract: A processing system includes a memory controller that preemptively exits a dynamic random access (DRAM) integrated circuit rank from a low power mode such as power down mode based on a predicted time when the memory controller will receive a request to access the DRAM rank. The memory controller tracks how long after a DRAM rank enters the low power mode before a request to access the DRAM rank is received by the memory controller. Based on a history of the timing of access requests, the memory controller predicts for each DRAM rank a predicted time reflecting how long after entering low power mode a request to access each DRAM rank is expected to be received. The memory controller speculatively exits the DRAM rank from the low power mode based on the predicted time and prior to receiving a request to access the DRAM IC rank.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: December 7, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Kedarnath Balakrishnan
  • Publication number: 20210374006
    Abstract: A memory controller interfaces with a dynamic random access memory (DRAM). The memory controller selectively places memory commands in a memory interface queue, and transmits the commands from the memory interface queue to a memory channel connected to at least one dynamic random access memory (DRAM). The transmitted commands are stored in a replay queue. A number of activate commands to a memory region of the DRAM is counted. Based on this count, a refresh control circuit signals that an urgent refresh command should be sent to the memory region. In response to detecting a designated type of error, a recovery sequence initiates to re-transmit memory commands from the replay queue. Designated error conditions can cause the recovery sequence to restart. If an urgent refresh command is pending when such a restart occurs, the recovery sequence is interrupted to allow the urgent refresh command to be sent.
    Type: Application
    Filed: May 29, 2020
    Publication date: December 2, 2021
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Jing Wang, James R. Magro, Kedarnath Balakrishnan
  • Publication number: 20210358540
    Abstract: A memory controller interfaces with a dynamic random access memory (DRAM) over a memory channel. A refresh control circuit monitors an activate counter which counts a rolling number of activate commands sent over the memory channel to a memory region of the DRAM. In response to the activate counter being above an intermediate management threshold value, the refresh control circuit only issue a refresh management (RFM) command if there is no REF command currently held at the refresh command circuit for the memory region.
    Type: Application
    Filed: May 15, 2020
    Publication date: November 18, 2021
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Kevin M. Brandl, Kedarnath Balakrishnan, Jing Wang, Guanhao Shen
  • Patent number: 11137941
    Abstract: Memory access commands are placed in a memory interface queue and transmitted from the memory interface queue to a heterogeneous memory channel coupled to a volatile dual in-line memory module (DIMM) and a non-volatile DIMM. Selected memory access commands that are placed in the memory interface queue are stored in a replay queue. The non-volatile reads that are placed in the memory interface queue are in a non-volatile command queue (NV queue). The method detects, based on information received over the heterogeneous memory channel, that an error has occurred requiring a recovery sequence. In response to the error, the method initiates the recovery sequence including (i) transmitting selected memory access commands that are stored in the replay queue, and (ii) transmitting non-volatile reads that are stored in the NV queue.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: October 5, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jing Wang, James R. Magro, Kedarnath Balakrishnan
  • Patent number: 11099786
    Abstract: A memory controller interfaces with a non-volatile storage class memory (SCM) module over a heterogeneous memory channel, and includes a command queue for receiving memory access commands. A memory interface queue is coupled to the command queue for holding outgoing commands. A non-volatile command queue is coupled to the command queue for storing non-volatile read commands that are placed in the memory interface queue. An arbiter selects entries from the command queue, and places them in the memory interface queue for transmission over a heterogeneous memory channel. A control circuit is coupled to the heterogeneous memory channel for receiving a ready response from the non-volatile SCM module indicating that responsive data is available for a non-volatile read command, and in response to receiving the ready response, causing a send command to be placed in the memory interface queue for commanding the non-volatile SCM module to send the responsive data.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: August 24, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: James R. Magro, Kedarnath Balakrishnan
  • Publication number: 20210200468
    Abstract: Memory access commands are placed in a memory interface queue and transmitted from the memory interface queue to a heterogeneous memory channel coupled to a volatile dual in-line memory module (DIMM) and a non-volatile DIMM. Selected memory access commands that are placed in the memory interface queue are stored in a replay queue. The non-volatile reads that are placed in the memory interface queue are in a non-volatile command queue (NV queue). The method detects, based on information received over the heterogeneous memory channel, that an error has occurred requiring a recovery sequence. In response to the error, the method initiates the recovery sequence including (i) transmitting selected memory access commands that are stored in the replay queue, and (ii) transmitting non-volatile reads that are stored in the NV queue.
    Type: Application
    Filed: December 30, 2019
    Publication date: July 1, 2021
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Jing Wang, James R. Magro, Kedarnath Balakrishnan
  • Publication number: 20210200618
    Abstract: A memory controller includes a command queue, a memory interface queue, and a non-volatile error reporting circuit. The command queue receives memory access commands including volatile reads, volatile writes, non-volatile reads, and non-volatile writes, and an output. The memory interface queue has an input coupled to the output of the command queue, and an output for coupling to a non-volatile storage class memory (SCM) module. The non-volatile error reporting circuit identifies error conditions associated with the non-volatile SCM module and maps the error conditions from a first number of possible error conditions associated with the non-volatile SCM module to a second, smaller number of virtual error types for reporting to an error monitoring module of a host operating system, the mapping based at least on a classification that the error condition will or will not have a deleterious effect on an executable process running on the host operating system.
    Type: Application
    Filed: December 30, 2019
    Publication date: July 1, 2021
    Applicant: Advanced Micro Devices, Inc.
    Inventors: James R. Magro, Kedarnath Balakrishnan, Vilas Sridharan
  • Publication number: 20210200695
    Abstract: Staging memory access requests includes receiving a memory access request directed to Dynamic Random Access Memory; storing the memory access request in a staging buffer; and moving the memory access request from the staging buffer to a command queue.
    Type: Application
    Filed: December 27, 2019
    Publication date: July 1, 2021
    Inventors: JAMES R. MAGRO, KEDARNATH BALAKRISHNAN, RAVINDRA N. BHARGAVA, GUANHAO SHEN
  • Publication number: 20210200649
    Abstract: A memory controller includes a command queue, a memory interface queue, at least one storage queue, and a replay control circuit. The command queue has a first input for receiving memory access commands. The memory interface queue receives commands selected from the command queue and couples to a heterogeneous memory channel which is coupled to at least one non-volatile storage class memory (SCM) module. The at least one storage queue stores memory access commands that are placed in the memory interface queue. The replay control circuit detects that an error has occurred requiring a recovery sequence, and in response to the error, initiates the recovery sequence. In the recovery sequence, the replay control circuit transmits selected memory access commands from the at least one storage queue by grouping non-volatile read commands together separately from all pending volatile reads, volatile writes, and non-volatile writes.
    Type: Application
    Filed: December 30, 2019
    Publication date: July 1, 2021
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Jing Wang, James R. Magro, Kedarnath Balakrishnan
  • Publication number: 20210200467
    Abstract: A memory controller interfaces with a non-volatile storage class memory (SCM) module over a heterogenous memory channel, and includes a command queue for receiving memory access commands. A memory interface queue is coupled to the command queue for holding outgoing commands. A non-volatile command queue is coupled to the command queue for storing non-volatile read commands that are placed in the memory interface queue. An arbiter selects entries from the command queue, and places them in the memory interface queue for transmission over a heterogenous memory channel. A control circuit is coupled to the heterogenous memory channel for receiving a ready response from the non-volatile SCM module indicating that responsive data is available for a non-volatile read command, and in response to receiving the ready response, causing a send command to be placed in the memory interface queue for commanding the non-volatile SCM module to send the responsive data.
    Type: Application
    Filed: December 30, 2019
    Publication date: July 1, 2021
    Applicant: Advanced Micro Devices, Inc.
    Inventors: James R. Magro, Kedarnath Balakrishnan
  • Publication number: 20210200694
    Abstract: Staging buffer arbitration includes: storing a plurality of memory access requests in a staging buffer; selecting a memory access request of the plurality of memory access requests from the staging buffer based on one or more arbitration rules; and moving the memory access request from the staging buffer to a command queue.
    Type: Application
    Filed: December 27, 2019
    Publication date: July 1, 2021
    Inventors: JAMES R. MAGRO, KEDARNATH BALAKRISHNAN, RAVINDRA N. BHARGAVA, GUANHAO SHEN
  • Publication number: 20210096750
    Abstract: Systems, apparatuses, and methods for performing scheduling memory requests for issue to two different memory types are disclosed. A computing system includes one or more clients for processing applications. A heterogeneous memory channel within a memory controller transfers memory traffic between the memory controller and a memory bus connected to each of a first memory and a second memory different from the first memory. The memory controller determines a next given point in time that does not already have read response data scheduled to be driven on the memory bus. The memory controller determines whether there is time to schedule a first memory access command for accessing the first memory and a second memory access command for accessing the second memory. If there is sufficient time for each, then one of the access commands is selected based on weighted criteria.
    Type: Application
    Filed: September 20, 2018
    Publication date: April 1, 2021
    Inventors: Kedarnath Balakrishnan, James Raymond Magro
  • Publication number: 20210073152
    Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. When a memory controller in a computing system determines a threshold number of memory access requests have not been sent to the memory device in a current mode of a read mode and a write mode, a first cost corresponding to a latency associated with sending remaining requests in either the read queue or the write queue associated with the current mode is determined. If the first cost exceeds the cost of a data bus turnaround, the cost of a data bus turnaround comprising a latency incurred when switching a transmission direction of the data bus from one direction to an opposite direction, then a second cost is determined for sending remaining memory access requests to the memory device. If the second cost does not exceed the cost of the data bus turnaround, then a time for the data bus turnaround is indicated and the current mode of the memory controller is changed.
    Type: Application
    Filed: November 20, 2020
    Publication date: March 11, 2021
    Inventors: Guanhao Shen, Ravindra N. Bhargava, Kedarnath Balakrishnan