Abstract: Staging buffer arbitration includes: storing a plurality of memory access requests in a staging buffer; selecting a memory access request of the plurality of memory access requests from the staging buffer based on one or more arbitration rules; and moving the memory access request from the staging buffer to a command queue.

Abstract: A memory controller interfaces with a non-volatile storage class memory (SCM) module over a heterogenous memory channel, and includes a command queue for receiving memory access commands. A memory interface queue is coupled to the command queue for holding outgoing commands. A non-volatile command queue is coupled to the command queue for storing non-volatile read commands that are placed in the memory interface queue. An arbiter selects entries from the command queue, and places them in the memory interface queue for transmission over a heterogenous memory channel. A control circuit is coupled to the heterogenous memory channel for receiving a ready response from the non-volatile SCM module indicating that responsive data is available for a non-volatile read command, and in response to receiving the ready response, causing a send command to be placed in the memory interface queue for commanding the non-volatile SCM module to send the responsive data.

Abstract: Memory access commands are placed in a memory interface queue and transmitted from the memory interface queue to a heterogeneous memory channel coupled to a volatile dual in-line memory module (DIMM) and a non-volatile DIMM. Selected memory access commands that are placed in the memory interface queue are stored in a replay queue. The non-volatile reads that are placed in the memory interface queue are in a non-volatile command queue (NV queue). The method detects, based on information received over the heterogeneous memory channel, that an error has occurred requiring a recovery sequence. In response to the error, the method initiates the recovery sequence including (i) transmitting selected memory access commands that are stored in the replay queue, and (ii) transmitting non-volatile reads that are stored in the NV queue.

Abstract: Systems, apparatuses, and methods for performing scheduling memory requests for issue to two different memory types are disclosed. A computing system includes one or more clients for processing applications. A heterogeneous memory channel within a memory controller transfers memory traffic between the memory controller and a memory bus connected to each of a first memory and a second memory different from the first memory. The memory controller determines a next given point in time that does not already have read response data scheduled to be driven on the memory bus. The memory controller determines whether there is time to schedule a first memory access command for accessing the first memory and a second memory access command for accessing the second memory. If there is sufficient time for each, then one of the access commands is selected based on weighted criteria.

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. When a memory controller in a computing system determines a threshold number of memory access requests have not been sent to the memory device in a current mode of a read mode and a write mode, a first cost corresponding to a latency associated with sending remaining requests in either the read queue or the write queue associated with the current mode is determined. If the first cost exceeds the cost of a data bus turnaround, the cost of a data bus turnaround comprising a latency incurred when switching a transmission direction of the data bus from one direction to an opposite direction, then a second cost is determined for sending remaining memory access requests to the memory device. If the second cost does not exceed the cost of the data bus turnaround, then a time for the data bus turnaround is indicated and the current mode of the memory controller is changed.

Abstract: Systems, apparatuses, and methods for identifying response data arriving out-of-order from two different memory types are disclosed. A computing system includes one or more clients for processing applications. A memory channel transfers memory traffic between a memory controller and a memory bus connected to each of a first memory and a second memory different from the first memory. The memory controller determines a given point in time when read data is to be scheduled to arrive on the memory bus from memory. The memory controller associates a unique identifier with the given point in time. The memory controller identifies a given command associated with the arriving read data based on the given point in time.

Abstract: A data processing system includes a memory channel, a memory coupled to the memory channel, and a data processor. The data processor is coupled to the memory channel and accesses the memory over the memory channel using a packet structure defining a plurality of commands and having corresponding address bits, data bits, and user bits. The data processor communicates with the memory over the memory channel using a first type of error code. In response to a write access request, the data processor calculates a different, second type of error code and appends each bit of the second type of error code as a corresponding one of the user bits. The memory stores the user bits in the memory in response to a write command, and transfers the user bits to the data processor in a read response packet in response to a read command.

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. When a memory controller in a computing system determines a threshold number of memory access requests have not been sent to the memory device in a current mode of a read mode and a write mode, a first cost corresponding to a latency associated with sending remaining requests in either the read queue or the write queue associated with the current mode is determined. If the first cost exceeds the cost of a data bus turnaround, the cost of a data bus turnaround comprising a latency incurred when switching a transmission direction of the data bus from one direction to an opposite direction, then a second cost is determined for sending remaining memory access requests to the memory device. If the second cost does not exceed the cost of the data bus turnaround, then a time for the data bus turnaround is indicated and the current mode of the memory controller is changed.

Abstract: In one form, a memory controller includes a command queue and an arbiter. The command queue receives and stores memory access requests. The arbiter includes a plurality of sub-arbiters for providing a corresponding plurality of sub-arbitration winners from among the memory access requests during a controller cycle, and for selecting among the plurality of sub-arbitration winners to provide a plurality of memory commands in a corresponding controller cycle. In another form, a data processing system includes a memory accessing agent for providing memory accesses requests, a memory system, and the memory controller coupled to the memory accessing agent and the memory system.

Abstract: A processing system includes a memory controller that preemptively exits a dynamic random access (DRAM) integrated circuit rank from a low power mode such as power down mode based on a predicted time when the memory controller will receive a request to access the DRAM rank. The memory controller tracks how long after a DRAM rank enters the low power mode before a request to access the DRAM rank is received by the memory controller. Based on a history of the timing of access requests, the memory controller predicts for each DRAM rank a predicted time reflecting how long after entering low power mode a request to access each DRAM rank is expected to be received. The memory controller speculatively exits the DRAM rank from the low power mode based on the predicted time and prior to receiving a request to access the DRAM IC rank.

Abstract: An electronic device including a memory functional block having multiple ranks of memory and a memory controller functional block coupled to the memory. The memory controller includes refresh logic that detects, based on buffered memory accesses for each rank of memory of the ranks of memory, two or more ranks of memory for which a refresh is to be performed during a refresh interval. Based at least in part on one or more properties of buffered memory accesses for the two or more ranks of memory, the refresh logic determines a refresh order for performing refreshes for the two or more ranks of memory during the refresh interval. The memory controller then performs, in the refresh order, refreshes for the two or more ranks of memory during the refresh interval.

Abstract: An electronic device including a memory functional block having multiple ranks of memory and a memory controller functional block coupled to the memory. The memory controller includes refresh logic that detects, based on buffered memory accesses for each rank of memory of the ranks of memory, two or more ranks of memory for which a refresh is to be performed during a refresh interval. Based at least in part on one or more properties of buffered memory accesses for the two or more ranks of memory, the refresh logic determines a refresh order for performing refreshes for the two or more ranks of memory during the refresh interval. The memory controller then performs, in the refresh order, refreshes for the two or more ranks of memory during the refresh interval.

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses in a computing system are disclosed. In various embodiments, a computing system includes computing resources and a memory controller coupled to a memory device. The memory controller determines a memory request targets a given rank of multiple ranks. The memory controller determines a predicted latency for the given rank as an amount of time the pending queue in the memory controller for storing outstanding memory requests does not store any memory requests targeting the given rank. The memory controller determines the total bank latency as an amount of time for refreshing a number of banks which have not yet been refreshed in the given rank with per-bank refresh operations. If there are no pending requests targeting the given rank, each of the predicted latency and the total bank latency is used to select between per-bank and all-bank refresh operations.

Abstract: In one form, an apparatus includes a memory controller. The memory controller includes a command queue and an arbiter. The command queue receives and stores memory access requests. The arbiter picks the memory access requests from the command queue based on a plurality of criteria, and provides picked memory access requests to a memory channel. The arbiter includes a streak counter for counting a number of consecutive memory access requests of a first type that the arbiter picks from the command queue. When the streak counter reaches a threshold, the arbiter suspends picking requests of the first type and picks at least one memory access request of a second type. The arbiter provides the at least one memory access request of the second type to the memory channel.

Abstract: A memory controller includes a host interface for receiving memory access requests including access addresses, a memory interface for providing memory accesses to a memory system, and an address decoder coupled to the host interface for programmably mapping the access addresses to selected ones of a plurality of regions. The address decoder is programmable to map the access addresses to a first region having a non-power-of-two size using a primary decoder and a secondary decoder each having power-of-two sizes, and providing a first region mapping signal in response. A command queue stores the memory access requests and region mapping signals. An arbiter picks the memory access requests from the command queue based on a plurality of criteria, which are evaluated based in part on the region mapping signals, and provides corresponding memory accesses to the memory interface in response.

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. In various embodiments, a computing system includes one or more computing resources and a memory controller coupled to a memory device. The memory controller determines a memory access request targets a given bank of multiple banks. An access history is updated for the given bank based on whether the memory access request hits on an open page within the given bank and a page hit rate for the given bank is determined. The memory controller sets an idle cycle limit based on the page hit rate. The idle cycle limit is a maximum amount of time the given bank will be held open before closing the given bank while the bank is idle. The idle cycle limit is based at least in part on a page hit rate for the bank.

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. When a memory controller in a computing system determines a threshold number of memory read requests have been sent to a memory device in a read mode of a data bus, the memory controller determines a threshold number of memory write requests to send to the memory device in an upcoming write mode is a number of outstanding memory write requests. Alternatively, the memory controller determines the threshold number of memory write requests to send to the memory device in an upcoming write mode is a maximum value of the number of outstanding memory write requests and a programmable value of the write burst length stored in a control register. Therefore, the write burst length is determined dynamically. Similarly, the read burst length is determined dynamically when the write mode ends.

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. When a memory controller in a computing system determines a threshold number of memory access requests have not been sent to the memory device in a current mode of a read mode and a write mode, a first cost corresponding to a latency associated with sending remaining requests in either the read queue or the write queue associated with the current mode is determined. If the first cost exceeds the cost of a data bus turnaround, the cost of a data bus turnaround comprising a latency incurred when switching a transmission direction of the data bus from one direction to an opposite direction, then a second cost is determined for sending remaining memory access requests to the memory device. If the second cost does not exceed the cost of the data bus turnaround, then a time for the data bus turnaround is indicated and the current mode of the memory controller is changed.

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses in a computing system are disclosed. In various embodiments, a computing system includes computing resources and a memory controller coupled to a memory device. The memory controller determines a memory request targets a given rank of multiple ranks. The memory controller determines a predicted latency for the given rank as an amount of time the pending queue in the memory controller for storing outstanding memory requests does not store any memory requests targeting the given rank. The memory controller determines the total bank latency as an amount of time for refreshing a number of banks which have not yet been refreshed in the given rank with per-bank refresh operations. If there are no pending requests targeting the given rank, each of the predicted latency and the total bank latency is used to select between per-bank and all-bank refresh operations.

Abstract: Systems, apparatuses, and methods for performing scheduling memory requests for issue to two different memory types are disclosed. A computing system includes one or more clients for processing applications. A heterogeneous memory channel within a memory controller transfers memory traffic between the memory controller and a memory bus connected to each of a first memory and a second memory different from the first memory. The memory controller determines a next given point in time that does not already have read response data scheduled to be driven on the memory bus. The memory controller determines whether there is time to schedule a first memory access command for accessing the first memory and a second memory access command for accessing the second memory. If there is sufficient time for each, then one of the access commands is selected based on weighted criteria.