Patents by Inventor Kei Nakamura

Kei Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090118263
    Abstract: An adenine compound represented by the formula (1): (1) [wherein A1 and A2 each independently represents an (un)substituted aromatic carbocycle or (un)substituted aromatic heterocycle; L1, L2, and L3 each independently represents alkylene or a single bond, provided that any methylene or methine group in L2 or L3 may be bonded to the nitrogen atom adjacent to L2 and L3 to form a 4- to 7-membered saturated nitrogenous heterocycle; L4 represents alkylene or a single bond; R1 represents (un)substituted alkyl, (un)substituted aryl, etc.; R2 represents hydrogen or (un)substituted alkyl; R3 represents (un)substituted alkyl, etc.; and X represents oxygen, etc.] or a pharmaceutically acceptable salt of the compound. The compound and salt are useful as a medicine.
    Type: Application
    Filed: September 20, 2006
    Publication date: May 7, 2009
    Applicants: Dainippon Sumitomo Pharma Co., Ltd., ASTRAZENECA AKTIEBOLAG
    Inventors: Kazuki Hashimoto, Tomoaki Nakamura, Kei Nakamura, Ayumu Kurimoto, Yoshiaki Isobe
  • Publication number: 20090105212
    Abstract: A novel adenine compound represented by the formula (1): wherein A represents an (un)substituted aromatic carbocycle or (un)substituted aromatic heterocycle; L1, L2, and L3 each independently represents linear or branched alkylene, etc.; R1 represents (un)substituted alkyl, (un)substituted aryl, etc.; R2 represents hydrogen or (un) substituted alkyl; R3 represents (un)substituted alkyl, etc., provided that R3 may be bonded to L2 or L3 to form a nitrogenous saturated heterocycle; and X represents oxygen, etc.; or a pharmaceutically acceptable salt of the compound. The compound and salt are useful as a medicine.
    Type: Application
    Filed: September 22, 2006
    Publication date: April 23, 2009
    Applicants: Dainippon Sumitomo Pharma Co., Ltd. a corporation of Japan, AstraZeneca Aktiebolag a corporation of Sweden
    Inventors: Yoshiaki Isobe, Ayumu Kurimoto, Kazuki Hashimoto, Tomoaki Nakamura, Kei Nakamura
  • Publication number: 20090082332
    Abstract: The present invention provides compounds of formula (I) wherein R1, Y1, X1, Z1, X2, Y2, A, Y3, n, R and R2 are as defined in the specification, processes for their preparation, pharmaceutical compositions containing them and their use in therapy.
    Type: Application
    Filed: September 20, 2006
    Publication date: March 26, 2009
    Inventors: Philip Abbot, Roger Victor Bonnert, Stephen Brough, Kamaldeep Chohan, Thomas McInally, Stephen Thom, Yoshiaki Isobe, Kei Nakamura, Shingo Tojo
  • Publication number: 20080269240
    Abstract: An adenine compound useful as a medicine represented by the following formula (1): [wherein R1 is halogen atom, optionally substituted alkyl group, optionally substituted aryl group, etc.; X is oxygen atom, sulfur atom, a single bond, etc.; A1 is optionally substituted and optionally saturated 4 to 8 membered heterocyclic group containing 1 to 2 hetero atoms selected from 1 to 3 nitrogen atoms, 0 to 1 oxygen atom, and 0 to 1 sulfur atom; A2 is optionally substituted 6 to 10 cyclic aromatic hydrocarbon group or optionally substituted 5 to 10 membered heterocyclic aromatic group; L1 and L2 are independently, substituted straight or branched alkylene or a single bond, etc.; L3 is optionally substituted straight or branched alkylene, etc.; R2 is hydrogen atom, optionally substituted alkyl group.] or its pharmaceutically acceptable salt.
    Type: Application
    Filed: September 21, 2006
    Publication date: October 30, 2008
    Applicants: Dainippon Sumitomo Pharma Co., Ltd. a corporation of Japan, AstraZeneca Aktiebolag A Corporation of Sweden
    Inventors: Kazuki Hashimoto, Tomoaki Nakamura, Kei Nakamura, Shingo Tojo, Ayumu Kurimoto, Yoshiaki Isobe, Hiroki Wada, Roger Bonnert
  • Publication number: 20080212991
    Abstract: An image forming apparatus which causes a long recording medium carrying a toner image thereon to pass between a fixing roller and a pressure roller to fix the toner image onto the long recording medium by means of the action of heat and pressure. The temperature of the fixing roller is prevented from being significantly reduced during operation of fixing the toner image, and thereby the occurrence of a toner image fixation failure is prevented. When the temperature of the fixing roller is reduced, in addition to a main heating member of heating means, electric power is also supplied from an auxiliary power source to an auxiliary heating member to cause the auxiliary heating member to generate heat.
    Type: Application
    Filed: November 6, 2007
    Publication date: September 4, 2008
    Inventor: Kei Nakamura
  • Publication number: 20080181645
    Abstract: A fixing device includes a fixing member, pressure member, first temperature detector, and pressure adjustment mechanism. The pressure member presses against the fixing member to form a nip though which a recording medium bearing a toner image thereon is conveyed. The first temperature detector detects a temperature of the fixing member. The pressure adjustment mechanism performs an adjustment to contact pressure between the fixing and pressure members to be lower than an appropriate pressure for image fixing at the detected temperature of the fixing roller or separation of the pressure roller from the fixing member for a part of a period between a time at which a tailing end of a precedent recording medium is conveyed out from the nip and a time at which a leading end of a following recording medium is conveyed into the nip when a plurality of recording media are successively conveyed through the nip.
    Type: Application
    Filed: November 7, 2007
    Publication date: July 31, 2008
    Inventor: Kei NAKAMURA
  • Publication number: 20080164236
    Abstract: An insulating layer made of an insulator film or the like is prepared. Then, a thin metal film and a thin copper film are formed in sequence on the insulating layer. The thin copper film is subsequently laminated with a dry film or the like, and exposed and developed to form a plating resist thereon that have patterns opposite to conductor patterns which are formed in a subsequent step. This is followed by forming conductor patterns made of copper, by electrolytic plating using an electrolytic copper sulfate plating solution, on the surfaces of the thin copper film where the plating resist is not formed. The plating resist is then removed by, for example, stripping. After this, the thin copper film is held at a temperature of not less than 200° C. and not more than 300° C. for approximately an hour to be thermally treated. Then, the thin copper film and the thin metal film are removed by chemical etching except the portions under the conductor patterns.
    Type: Application
    Filed: December 13, 2007
    Publication date: July 10, 2008
    Applicant: NITTO DENKO CORPORATION
    Inventors: Kei NAKAMURA, Takeshi YAMATO
  • Publication number: 20070108631
    Abstract: A wired circuit board is provided having a high-reliability conductive pattern formed thereon and mounting an electronic component thereon with high accuracy, and a method is provided for manufacturing the wired circuit board and mounting the electronic component thereon. An insulating layer including a mounting portion is formed on a metal supporting layer having a specular gloss of 150 to 500% at an incidence angle of 45°. A conductive pattern is formed on the insulating layer. By a reflection-type optical sensor, a defective shape of the conductive pattern is inspected. Then, an opening is formed by etching the portion of the metal supporting layer which is overlapping the mounting portion such that the mounting portion of the insulating layer exposed by etching has a haze value of 20 to 50%, whereby a TAB tape carrier is obtained.
    Type: Application
    Filed: November 13, 2006
    Publication date: May 17, 2007
    Applicant: Nitto Denko Corporation
    Inventors: Kei Nakamura, Hitoshi Ishizaka
  • Publication number: 20070047989
    Abstract: An image forming apparatus includes a fixing apparatus for fixing a toner image onto a recording medium by applying pressure and heat to toner provided on the surface of the recording medium. The fixing apparatus includes a fixing member, a pressing member for pressing against the fixing member, a temperature detecting part for detecting the temperature of the fixing member, and a heating member including a main heating member and an auxiliary heating member for heating the fixing member, the main heating member being heated by obtaining power from a main power supply, the auxiliary heating member being heated by obtaining power from an auxiliary power supply.
    Type: Application
    Filed: August 22, 2006
    Publication date: March 1, 2007
    Inventors: Kei Nakamura, Nobuyuki Satoh
  • Publication number: 20070023876
    Abstract: To provide a TAB tape carrier that can provide improved adhesion of a conductive pattern to an insulating base layer, while strengthening a connection between gold terminals of a semiconductor device and connection terminals covered with a tin plating layer, and can prevent the conductive pattern from sinking into the insulating base layer. In the TAB tape carrier, an insulating base layer is formed by laminating a thermoplastic polyimide resin layer of 4 ?m thick or less on a thermosetting polyimide resin layer, and a conductive pattern having inner leads covered with a tin plating layer is formed on a surface of the thermoplastic polyimide resin layer. In this TAB tape carrier, even when the gold terminals of the semiconductor device are press-bonded to the inner leads covered with the tin plating layer at high temperatures and pressures, the conductive pattern can be prevented from sinking into the insulating base layer.
    Type: Application
    Filed: July 25, 2006
    Publication date: February 1, 2007
    Applicant: Nitto Denko Corporation
    Inventors: Kei Nakamura, Yasuto Ishimaru
  • Publication number: 20070000689
    Abstract: In an outer lead portion, outer lead wirings are provided on one surface of a base insulating layer and a plurality of metal substrates are provided on the opposite surface thereof. The plurality of metal substrates are provided with predetermined spacings therebetween. The outer lead wirings are not provided on the areas on the surface opposite to the areas on the other surface of the base insulating layer on which the slits are provided between the metal substrates. Metals such as stainless steel, copper or copper alloy can be used for the metal substrates. Coefficient of linear expansion of each metal substrate is preferably equal to that of the base insulating layer.
    Type: Application
    Filed: June 29, 2006
    Publication date: January 4, 2007
    Applicant: NITTO DENKO CORPORATION
    Inventors: Yasuto ISHIMARU, Kei NAKAMURA
  • Publication number: 20060000637
    Abstract: An insulating layer made of an insulator film or the like is prepared. Then, a thin metal film and a thin copper film are formed in sequence on the insulating layer. The thin copper film is subsequently laminated with a dry film or the like, and exposed and developed to form a plating resist thereon that have patterns opposite to conductor patterns which are formed in a subsequent step. This is followed by forming conductor patterns made of copper, by electrolytic plating using an electrolytic copper sulfate plating solution, on the surfaces of the thin copper film where the plating resist is not formed. The plating resist is then removed by, for example, stripping. After this, the thin copper film is held at a temperature of not less than 200° C. and not more than 300° C. for approximately an hour to be thermally treated. Then, the thin copper film and the thin metal film are removed by chemical etching except the portions under the conductor patterns.
    Type: Application
    Filed: July 1, 2005
    Publication date: January 5, 2006
    Inventors: Kei Nakamura, Takeshi Yamato
  • Publication number: 20050260391
    Abstract: A wired circuit board on which a highly reliable conductor pattern is formed, to allow an electronic component to be mounted on it with improved accuracy. An insulating layer 3 is formed on a metal supporting layer 2 having a degree of surface brilliancy of 150-500% in such a manner as to have a haze value of 20-50% and also a conductor pattern 4 is formed on the insulating layer 3, thereby producing a TAB tape carrier 1. In this TAB tape carrier 1, since the metal supporting layer 2 has a specified degree of surface brilliancy of 500% or less, the pattern design of the conductor pattern 4 is optically examined to determine whether it is good or bad with high accuracy.
    Type: Application
    Filed: May 19, 2005
    Publication date: November 24, 2005
    Applicant: Nitto Denko Corporation
    Inventors: Kei Nakamura, Hitoshi Ishizaka, Atsushi Yoshida, Takami Hikita
  • Publication number: 20050244620
    Abstract: A wired circuit board which is formed so that even when a wired circuit pattern is formed at a fine pitch and then a tin plating layer is formed on the wired circuit pattern by the electroless tin plating, a wiring of the wired circuit pattern can be prevented from being stripped, and a production method of the same wired circuit board. After a thin metal film 2 formed of nickel-chromium alloy having a chromium content of 8-20 weight % is formed on an insulating layer 1, a wired circuit pattern 4 of copper is formed on the thin metal film 2. Then, a tin plating layer 5 is formed on exposed surfaces of the wired circuit pattern 4 by electroless tin plating.
    Type: Application
    Filed: April 19, 2005
    Publication date: November 3, 2005
    Applicant: Nitto Denko Corporation
    Inventors: Makoto Tsunekawa, Kei Nakamura, Keiko Toyozawa, Takeshi Yamato, Toshikazu Baba
  • Publication number: 20050182505
    Abstract: The invention is intended to provide a building sequence planning system for an automobile production line, which can prepare an efficient building sequence. The system comprises an input unit (1) for inputting information of vehicles to be manufactured, a processing unit (3) for deciding an optimum building sequence based on the vehicle information inputted through the input unit (1), and an output unit (5) for externally outputting a building sequence schedule decided by the processing unit (3). The processing unit (3) prepares a vehicle building sequence, determines a degree of dissatisfaction of the prepared building sequence, as a penalty value, in accordance with restriction conditions which are inputted through the input unit (1) and are imposed when building the vehicles into work, and decides a building sequence with a minimum penalty by preparing a plurality of building sequences and determining the penalty value for each building sequence with respect to the restriction conditions.
    Type: Application
    Filed: February 27, 2003
    Publication date: August 18, 2005
    Inventors: Hitoshi Onizawa, Masanori Sato, Kei Nakamura, Atsumi Ichikawa, Hiroshi Soejima, Shinichi Sakagami, Yutaka Sanada
  • Patent number: 6887560
    Abstract: A multilayer flexible wired circuit board that can provide high density wiring and also can provide reduction in thickness and size, and a producing method thereof. A four-layered flexible wired circuit board is produced by preparing a double-sided substrate in which a first conductor layer and a second conductor layer are laminated on both sides of a first insulating layer; preparing a first single-sided substrate in which a third conductor layer is laminated on one surface of a second insulating layer and a second single-sided substrate in which a fourth conductor layer is laminated on one surface of a third insulating layer; bonding the first conductor layer and the third conductor layer to each other through a first thermosetting adhesive layer; and bonding the second conductor layer and the fourth conductor layer to each other through a second thermosetting adhesive layer.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: May 3, 2005
    Assignee: Nitto Denko Corporation
    Inventors: Kei Nakamura, Satoshi Tanigawa, Hiroshi Yamazaki, Mineyoshi Hasegawa
  • Publication number: 20050079652
    Abstract: A method of producing a multilayer wired circuit board that can suppress making gouge in an adhesive layer when a hole is formed by irradiation with a laser beam, to provide a smoothened inside surface of the hole so as to provide enhanced reliability of electrical connection. A first substrate 4 having the structure wherein a first metal foil 2 and a second metal foil 3 are formed on both sides of a first insulating layer 1 and a second substrate 7 having the structure wherein a third metal foil 6 is formed on a single side of a second insulating layer 5 are prepared, separately. Then, the first metal foil 2 of the first substrate 4 and the second insulating layer 5 of the second substrate 7 are bonded together through an adhesive layer 8. Thereafter, the resultant laminate is irradiated with a laser beam emitting from the first substrate 4 side toward the second substrate 7 side, to form a through hole 9.
    Type: Application
    Filed: October 7, 2004
    Publication date: April 14, 2005
    Inventors: Mineyoshi Hasegawa, Kei Nakamura, Toshikazu Baba
  • Patent number: 6851599
    Abstract: A method of producing a multilayer wired circuit board that can provide sufficient adhesion strength of the interface between a conductor layer and a thermosetting adhesive layer laminated, to provide improvement in connection strength between the conductor layers and thus improvement in reliability. In this method, after a thermosetting adhesive layer is formed on a first conductor layer, an opening is formed in the thermosetting adhesive layer and solder powders are charged in the opening at normal temperature. Sequentially, a second conductor layer is formed on the thermosetting adhesive layer including the opening filled with the solder powders. Thereafter, the solder powders are melted by heating, to electrically connect between the first conductor layer and the second conductor layer.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: February 8, 2005
    Assignee: Nitto Denko Corporation
    Inventors: Kei Nakamura, Satoshi Tanigawa, Shinya Oota
  • Publication number: 20040035520
    Abstract: A multilayer flexible wired circuit board that can provide high density wiring and also can provide reduction in thickness and size, and a producing method thereof. A four-layered flexible wired circuit board is produced by preparing a double-sided substrate in which a first conductor layer and a second conductor layer are laminated on both sides of a first insulating layer; preparing a first single-sided substrate in which a third conductor layer is laminated on one surface of a second insulating layer and a second single-sided substrate in which a fourth conductor layer is laminated on one surface of a third insulating layer; bonding the first conductor layer and the third conductor layer to each other through a first thermosetting adhesive layer; and bonding the second conductor layer and the fourth conductor layer to each other through a second thermosetting adhesive layer.
    Type: Application
    Filed: March 5, 2003
    Publication date: February 26, 2004
    Inventors: Kei Nakamura, Satoshi Tanigawa, Hiroshi Yamazaki, Mineyoshi Hasegawa
  • Publication number: 20040011855
    Abstract: A method of producing a multilayer wired circuit board that can provide sufficient adhesion strength of the interface between a conductor layer and a thermosetting adhesive layer laminated, to provide improvement in connection strength between the conductor layers and thus improvement in reliability. In this method, after a thermosetting adhesive layer is formed on a first conductor layer, an opening is formed in the thermosetting adhesive layer and solder powders are charged in the opening at normal temperature. Sequentially, a second conductor layer is formed on the thermosetting adhesive layer including the opening filled with the solder powders. Thereafter, the solder powders are melted by heating, to electrically connect between the first conductor layer and the second conductor layer.
    Type: Application
    Filed: March 5, 2003
    Publication date: January 22, 2004
    Inventors: Kei Nakamura, Satoshi Tanigawa, Shinya Oota