Patents by Inventor Kei Nakamura

Kei Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040011855
    Abstract: A method of producing a multilayer wired circuit board that can provide sufficient adhesion strength of the interface between a conductor layer and a thermosetting adhesive layer laminated, to provide improvement in connection strength between the conductor layers and thus improvement in reliability. In this method, after a thermosetting adhesive layer is formed on a first conductor layer, an opening is formed in the thermosetting adhesive layer and solder powders are charged in the opening at normal temperature. Sequentially, a second conductor layer is formed on the thermosetting adhesive layer including the opening filled with the solder powders. Thereafter, the solder powders are melted by heating, to electrically connect between the first conductor layer and the second conductor layer.
    Type: Application
    Filed: March 5, 2003
    Publication date: January 22, 2004
    Inventors: Kei Nakamura, Satoshi Tanigawa, Shinya Oota
  • Patent number: 6462282
    Abstract: A circuit board for mounting a bare chip in the form of a flip chip. A metallic foil for protecting circuits in a state insulated therefrom is arranged in an area where the bare chip is located.
    Type: Grant
    Filed: June 23, 1999
    Date of Patent: October 8, 2002
    Assignee: Nitto Denko Corporation
    Inventors: Yasushi Inoue, Masakazu Sugimoto, Megumu Nagasawa, Kei Nakamura
  • Patent number: 6373000
    Abstract: A double-sided circuit board of which a solder conductor is prevented from deformation in a cycling test so as to maintain high connection reliability, comprises an insulating layer 2 made of an organic high molecular weight resin and a circuit 3 provided on each side of the insulating layer 2, the circuits 3 on both sides being electrically connected through via-holes filled with a conductor 4 made of solder having a metal powder 6 dispersed therein.
    Type: Grant
    Filed: December 14, 2000
    Date of Patent: April 16, 2002
    Assignee: Nitto Denko Corporation
    Inventors: Kei Nakamura, Masakazu Sugimoto, Yasushi Inoue, Megumu Nagasawa, Takuji Okeyui, Masayuki Kaneto, Shinya Ota
  • Patent number: 6335076
    Abstract: A plurality of double-sided circuit boards 1 in which a circuit 4 is provided on either side of an insulating layer 3 comprising an organic high molecular resin with an alloy foil 2 as a basic substance, and two circuits 4 are electrically connected by a via with a soldered conductor 5a filled therein are laminated via an adhesive layer 6. The adhesive layer 6 has a bore opened at a predetermined position of a portion in direct contact with the circuits 4 of two double-sided circuit boards 1. A bore portion is provided with a soldered conductor 7. The circuits 4 of the two double-sided circuit boards 1 are electrically connected by the soldered conductor 7.
    Type: Grant
    Filed: July 13, 2000
    Date of Patent: January 1, 2002
    Assignee: Nitto Denko Corporation
    Inventors: Kei Nakamura, Masakazu Sugimoto, Yasushi Inoue, Megumu Nagasawa, Takuji Okeyui
  • Patent number: 6333469
    Abstract: A wafer-scale package structure in which a circuit board for rearranging electrode pads of a wafer is laminated on the wafer integrally. The circuit board can be divided into individual chip-size packages (CSPS) and which includes a layer of polyimide resin, and connection between the wafer and the circuit board is performed by solder bump, while the circuit board is stuck on the wafer with an adhesive.
    Type: Grant
    Filed: July 15, 1999
    Date of Patent: December 25, 2001
    Assignee: Nitto Denko Corporation
    Inventors: Yasushi Inoue, Masakazu Sugimoto, Megumu Nagasawa, Takuji Okeyui, Kei Nakamura
  • Patent number: 6310391
    Abstract: The present invention provides a mounted structure of circuit board which can be prepared by a simple method and exhibits a good heat dissipation from chip and undergoes relaxed heat stress and a multi-layer circuit board to be incorporated in the mounted structure. A novel mounted structure of circuit board is provided comprising a core material embedded in an insulating layer, said core material having a metal layer with a heat conductivity of not less than 100 W/m·K provided on at least one side of an Ni—Fe alloy foil, said insulating layer comprising a wire conductor provided and a semiconductor element mounted on at least one side thereof, characterized in that a solder metal member for heat conduction is provided interposed between said semiconductor element and said core material so that said semiconductor element and said core material are connected to each other.
    Type: Grant
    Filed: June 17, 1999
    Date of Patent: October 30, 2001
    Assignee: Nitto Denko Corporation
    Inventors: Megumu Nagasawa, Masakazu Sugimoto, Yasushi Inoue, Kei Nakamura
  • Patent number: 6258449
    Abstract: A low-thermal expansion circuit board comprising an insulating layer made of an organic polymer having thereon a wiring conductor for bare chip mounting, wherein the wiring conductor is an iron-nickel-based alloy layer having a copper layer on at least one side thereof; and a low-thermal expansion multilayer circuit board having a plurality of the low-thermal expansion circuit boards via an adhesive layer, the adhesive layer having through-holes filled with solder to connect the circuits layers.
    Type: Grant
    Filed: June 9, 1999
    Date of Patent: July 10, 2001
    Assignee: Nitto Denko Corporation
    Inventors: Megumu Nagasawa, Masakazu Sugimoto, Yasushi Inoue, Kei Nakamura
  • Publication number: 20010004944
    Abstract: A double-sided circuit board of which a solder conductor is prevented from deformation in a cycling test so as to maintain high connection reliability, comprises an insulating layer 2 made of an organic high molecular weight resin and a circuit 3 provided on each side of the insulating layer 2, the circuits 3 on both sides being electrically connected through via-holes filled with a conductor 4 made of solder having a metal powder 6 dispersed therein.
    Type: Application
    Filed: December 14, 2000
    Publication date: June 28, 2001
    Inventors: Kei Nakamura, Masakazu Sugimoto, Yasushi Inoue, Megumu Nagasawa, Takuji Okeyui, Masayuki Kaneto, Shinya Ota
  • Patent number: 5437047
    Abstract: A program run information gathering system for a multiprocessor system gathers program run information inclusive of an interrupt masked kernel program from all the processors of the multiprocessor system for evaluation of distribution of program runs in the system, while protecting data as gathered against being lost even upon occurrence of a crash in a processor.
    Type: Grant
    Filed: May 27, 1994
    Date of Patent: July 25, 1995
    Assignee: Fujitsu Limited
    Inventor: Kei Nakamura
  • Patent number: 5386544
    Abstract: A data processing system for gaining access to resources by performing message communications with resource managers within a range of given capabilities, in which given capabilities are saved in a non-volatile memory at the start-up of a currently operating process so that when recovery is attempted at the time of a failure, a standby process can take over the resource access by fetching the capabilities from the non-volatile memory and restoring them.
    Type: Grant
    Filed: May 21, 1992
    Date of Patent: January 31, 1995
    Assignee: Fujitsu, Ltd.
    Inventor: Kei Nakamura