Patents by Inventor Keiichi SAWA

Keiichi SAWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220077183
    Abstract: In one embodiment, a semiconductor device includes a substrate, and a plurality of electrode layers provided separately from each other in a first direction perpendicular to a surface of the substrate. The device further includes a first insulator, a charge storage layer, a second insulator, a first semiconductor region including silicon, and a second semiconductor region including silicon and carbon, which are provided in order on side faces of the electrode layers, wherein an interface between the first semiconductor region and the second insulator includes fluorine.
    Type: Application
    Filed: March 10, 2021
    Publication date: March 10, 2022
    Applicant: Kioxia Corporation
    Inventors: Takaumi MORITA, Hisashi OKUCHI, Keiichi SAWA, Hiroyuki YAMASHITA, Toshiaki YANASE, Tsubasa IMAMURA
  • Publication number: 20210305431
    Abstract: A semiconductor device of an embodiment includes a first electrode, a second electrode, a first metallic region provided between the first electrode and the second electrode and includes at least one metallic element selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), aluminum (Al), magnesium (Mg), manganese (Mn), titanium (Ti), tungsten (W), molybdenum (Mo), and tin (Sn), a second metallic region provided between the first metallic region and the second electrode and includes the at least one metallic element, a semiconductor region provided between the first metallic region and the second metallic region and includes the at least one metallic element and oxygen (O), an insulating region provided between the first metallic region and the second metallic region and is surrounded by the semiconductor region, a gate electrode surrounding the semiconductor region, and a gate insulating layer provided between the semiconductor region and the gate electrode.
    Type: Application
    Filed: September 16, 2020
    Publication date: September 30, 2021
    Applicant: Kioxia Corporation
    Inventors: Tomoki ISHIMARU, Shinji MORI, Kazuhiro MATSUO, Keiichi SAWA, Akifumi GAWASE
  • Publication number: 20210225859
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of U-shaped memory strings, each of the plurality of U-shaped memory strings including a first columnar body, a second columnar body, and a conductive connection body. The conductive connection body connects the first columnar body and the second columnar body. A plurality of first memory cells are connected in series in the first columnar body and are composed of a plurality of first conductive layers, a first inter-gate insulating film, a plurality of first floating electrodes, a first tunnel insulating film, and a first memory channel layer. The plurality of first floating electrodes are separated from the plurality of first conductive layers by the first inter-gate insulating film. A plurality of second memory cells are connected in series in the second columnar body, similarly to the plurality of first memory cells.
    Type: Application
    Filed: April 7, 2021
    Publication date: July 22, 2021
    Applicant: Toshiba Memory Corporatiion
    Inventor: Keiichi SAWA
  • Patent number: 11011532
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of U-shaped memory strings, each of the plurality of U-shaped memory strings including a first columnar body, a second columnar body, and a conductive connection body. The conductive connection body connects the first columnar body and the second columnar body. A plurality of first memory cells are connected in series in the first columnar body and are composed of a plurality of first conductive layers, a first inter-gate insulating film, a plurality of first floating electrodes, a first tunnel insulating film, and a first memory channel layer. The plurality of first floating electrodes are separated from the plurality of first conductive layers by the first inter-gate insulating film. A plurality of second memory cells are connected in series in the second columnar body, similarly to the plurality of first memory cells.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: May 18, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Keiichi Sawa
  • Publication number: 20210118906
    Abstract: In one embodiment, a semiconductor device includes a substrate, insulating films and first films alternately stacked on the substrate, at least one of the first films including an electrode layer and a charge storage layer provided on a face of the electrode layer via a first insulator, and a semiconductor layer provided on a face of the charge storage layer via a second insulator. The device further includes at least one of a first portion including nitrogen and provided between the first insulator and the charge storage layer with an air gap provided in the first insulator, a second portion including nitrogen, provided between the charge storage layer and the second insulator, and including a portion protruding toward the charge storage layer, and a third portion including nitrogen and provided between the second insulator and the semiconductor layer with an air gap provided in the first insulator.
    Type: Application
    Filed: December 29, 2020
    Publication date: April 22, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Keiichi SAWA, Kazuhiro MATSUO, Kazuhisa MATSUDA, Hiroyuki YAMASHITA, Yuta SAITO, Shinji MORI, Masayuki TANAKA, Kenichiro TORATANI, Atsushi TAKAHASHI, Shouji HONDA
  • Patent number: 10964716
    Abstract: A semiconductor device comprises a substrate. A plurality of electrode layers and a plurality of insulating layers are formed in an alternating stack above the substrate. A semiconductor column extends through the plurality of electrode layers and the plurality of insulating layers. The semiconductor column comprises a single-crystal semiconductor material on an outer peripheral surface facing the electrode and insulating layers. First insulating films are formed between the semiconductor column and the electrode layers. The first insulating films are spaced from each other along the column length. Each first insulating film corresponds to one electrode layer. A charge storage layer is between each of the first insulating films and the electrode layers. A second insulating film is between the charge storage layer and each of the electrode layers.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: March 30, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinji Mori, Kazuhiro Matsuo, Yuta Saito, Keiichi Sawa, Kazuhisa Matsuda, Atsushi Takahashi, Masayuki Tanaka, Kenichiro Toratani
  • Patent number: 10923487
    Abstract: A semiconductor memory device includes a channel layer and a gate electrode. A first insulating layer is between the semiconductor layer and the gate electrode. A second insulating layer is between the first insulating layer and the gate electrode. A storage region is between the first insulating layer and the second insulating layer. The storage region comprises metal or semiconductor material. A coating layer comprises silicon and nitrogen and surrounds the storage region. The coating layer is between the storage region and the second insulating layer and between the storage region and the first insulating layer.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: February 16, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroyuki Yamashita, Shinji Mori, Keiichi Sawa, Kazuhiro Matsuo, Kazuhisa Matsuda, Yuta Saito, Atsushi Takahashi, Masayuki Tanaka
  • Patent number: 10910401
    Abstract: In one embodiment, a semiconductor device includes a substrate, insulating films and first films alternately stacked on the substrate, at least one of the first films including an electrode layer and a charge storage layer provided on a face of the electrode layer via a first insulator, and a semiconductor layer provided on a face of the charge storage layer via a second insulator. The device further includes at least one of a first portion including nitrogen and provided between the first insulator and the charge storage layer with an air gap provided in the first insulator, a second portion including nitrogen, provided between the charge storage layer and the second insulator, and including a portion protruding toward the charge storage layer, and a third portion including nitrogen and provided between the second insulator and the semiconductor layer with an air gap provided in the first insulator.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: February 2, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Keiichi Sawa, Kazuhiro Matsuo, Kazuhisa Matsuda, Hiroyuki Yamashita, Yuta Saito, Shinji Mori, Masayuki Tanaka, Kenichiro Toratani, Atsushi Takahashi, Shouji Honda
  • Publication number: 20210013225
    Abstract: In one embodiment, a semiconductor storage device includes a stacked body in which a plurality of conducting layers are stacked through a plurality of insulating layers in a first direction, a semiconductor layer penetrating the stacked body, extending in the first direction and including metal atoms, and a memory film including a first insulator, a charge storage layer and a second insulator that are provided between the stacked body and the semiconductor layer. The semiconductor layer surrounds a third insulator penetrating the stacked body and extending in the first direction, and at least one crystal grain in the semiconductor layer has a shape surrounding the third insulator.
    Type: Application
    Filed: March 5, 2020
    Publication date: January 14, 2021
    Applicant: Kioxia Corporation
    Inventors: Yuta SAITO, Shinji MORI, Atsushi TAKAHASHI, Toshiaki YANASE, Keiichi SAWA, Kazuhiro MATSUO, Hiroyuki YAMASHITA
  • Publication number: 20200373328
    Abstract: A semiconductor device includes a semiconductor layer containing metal atoms, a charge storage layer provided on a surface of the semiconductor layer via a first insulating film, and an electrode layer provided on a surface of the charge storage layer via a second insulating film. The thickness of the first insulating film is 5 nm or more and 10 nm or less. The concentration of the metal atoms in the semiconductor layer is 5.0×1017 [EA/cm3] or higher and 1.3×1020 [EA/cm3] or lower.
    Type: Application
    Filed: August 14, 2020
    Publication date: November 26, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Yuta SAITO, Shinji MORI, Keiichi SAWA, Kazuhisa MATSUDA, Kazuhiro MATSUO, Hiroyuki YAMASHITA
  • Publication number: 20200295035
    Abstract: In one embodiment, a semiconductor device includes a substrate, insulating films and first films alternately stacked on the substrate, at least one of the first films including an electrode layer and a charge storage layer provided on a face of the electrode layer via a first insulator, and a semiconductor layer provided on a face of the charge storage layer via a second insulator. The device further includes at least one of a first portion including nitrogen and provided between the first insulator and the charge storage layer with an air gap provided in the first insulator, a second portion including nitrogen, provided between the charge storage layer and the second insulator, and including a portion protruding toward the charge storage layer, and a third portion including nitrogen and provided between the second insulator and the semiconductor layer with an air gap provided in the first insulator.
    Type: Application
    Filed: September 3, 2019
    Publication date: September 17, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Keiichi SAWA, Kazuhiro MATSUO, Kazuhisa MATSUDA, Hiroyuki YAMASHITA, Yuta SAITO, Shinji MORI, Masayuki TANAKA, Kenichiro TORATANI, Atsushi TAKAHASHI, Shouji HONDA
  • Patent number: 10777573
    Abstract: A semiconductor device includes a semiconductor layer containing metal atoms, a charge storage layer provided on a surface of the semiconductor layer via a first insulating film, and an electrode layer provided on a surface of the charge storage layer via a second insulating film. The thickness of the first insulating film is 5 nm or more and 10 nm or less. The concentration of the metal atoms in the semiconductor layer is 5.0×1017 [EA/cm3] or higher and 1.3×1020 [EA/cm3] or lower.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: September 15, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuta Saito, Shinji Mori, Keiichi Sawa, Kazuhisa Matsuda, Kazuhiro Matsuo, Hiroyuki Yamashita
  • Publication number: 20200091172
    Abstract: A semiconductor device comprises a substrate. A plurality of electrode layers and a plurality of insulating layers are formed in an alternating stack above the substrate. A semiconductor column extends through the plurality of electrode layers and the plurality of insulating layers. The semiconductor column comprises a single-crystal semiconductor material on an outer peripheral surface facing the electrode and insulating layers. First insulating films are formed between the semiconductor column and the electrode layers. The first insulating films are spaced from each other along the column length. Each first insulating film corresponds to one electrode layer. A charge storage layer is between each of the first insulating films and the electrode layers. A second insulating film is between the charge storage layer and each of the electrode layers.
    Type: Application
    Filed: February 14, 2019
    Publication date: March 19, 2020
    Inventors: Shinji MORI, Kazuhiro MATSUO, Yuta SAITO, Keiichi SAWA, Kazuhisa MATSUDA, Atsushi TAKAHASHI, Masayuki TANAKA, Kenichiro TORATANI
  • Publication number: 20200091165
    Abstract: A semiconductor memory device includes a channel layer and a gate electrode. A first insulating layer is between the semiconductor layer and the gate electrode. A second insulating layer is between the first insulating layer and the gate electrode. A storage region is between the first insulating layer and the second insulating layer. The storage region comprises metal or semiconductor material. A coating layer comprises silicon and nitrogen and surrounds the storage region. The coating layer is between the storage region and the second insulating layer and between the storage region and the first insulating layer.
    Type: Application
    Filed: February 27, 2019
    Publication date: March 19, 2020
    Inventors: Hiroyuki YAMASHITA, Shinji MORI, Keiichi SAWA, Kazuhiro MATSUO, Kazuhisa MATSUDA, Yuta SAITO, Atsushi TAKAHASHI, Masayuki TANAKA
  • Publication number: 20200043940
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of U-shaped memory strings, each of the plurality of U-shaped memory strings including a first columnar body, a second columnar body, and a conductive connection body. The conductive connection body connects the first columnar body and the second columnar body. A plurality of first memory cells are connected in series in the first columnar body and are composed of a plurality of first conductive layers, a first inter-gate insulating film, a plurality of first floating electrodes, a first tunnel insulating film, and a first memory channel layer. The plurality of first floating electrodes are separated from the plurality of first conductive layers by the first inter-gate insulating film. A plurality of second memory cells are connected in series in the second columnar body, similally to the plurality of first memoriy cells.
    Type: Application
    Filed: October 15, 2019
    Publication date: February 6, 2020
    Applicant: Toshiba Memory Corporation
    Inventor: Keiichi SAWA
  • Patent number: 10522596
    Abstract: In one embodiment, a semiconductor storage device includes a first interconnect extending in a first direction, a plurality of second interconnects extending in a second direction different from the first direction, and a plurality of first insulators provided alternately with the second interconnects. The device further includes a resistance change film provided between the first interconnect and at least one of the second interconnects and including a first metal layer or a first semiconductor layer that includes a first face provided on a first interconnect side and a second face provided on a second interconnect side, at least any of the first face and the second face having a curved plane shape.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: December 31, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Keiichi Sawa, Kazuhisa Matsuda, Atsushi Takahashi, Takaumi Morita, Masayuki Tanaka, Shinji Mori, Kazuhiro Matsuo, Yuta Saito, Kenichiro Toratani, Hisashi Okuchi
  • Publication number: 20190371810
    Abstract: A semiconductor device includes a semiconductor layer containing metal atoms, a charge storage layer provided on a surface of the semiconductor layer via a first insulating film, and an electrode layer provided on a surface of the charge storage layer via a second insulating film. The thickness of the first insulating film is 5 nm or more and 10 nm or less. The concentration of the metal atoms in the semiconductor layer is 5.0×1017 [EA/cm3] or higher and 1.3×1020 [EA/cm3] or lower.
    Type: Application
    Filed: February 25, 2019
    Publication date: December 5, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Yuta SAITO, Shinji MORI, Keiichi SAWA, Kazuhisa MATSUDA, Kazuhiro MATSUO, Hiroyuki YAMASHITA
  • Patent number: 10490563
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of U-shaped memory strings, each of the plurality of U-shaped memory strings including a first columnar body, a second columnar body, and a conductive connection body. The conductive connection body connects the first columnar body and the second columnar body. A plurality of first memory cells are connected in series in the first columnar body and are composed of a plurality of first conductive layers, a first inter-gate insulating film, a plurality of first floating electrodes, a first tunnel insulating film, and a first memory channel layer. The plurality of first floating electrodes are separated from the plurality of first conductive layers by the first inter-gate insulating film. A plurality of second memory cells are connected in series in the second columnar body, similarly to the plurality of first memory cells.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: November 26, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Keiichi Sawa
  • Patent number: 10396280
    Abstract: A semiconductor memory device includes a plurality of first interconnections extending in a first direction, and a second interconnection extending in a second direction different from the first direction. The device further includes a resistance change film provided between the plurality of first interconnections and the second interconnection, the resistance change film including (a) silicon and a semiconductor layer including one or more elements selected from among oxygen, carbon, nitrogen, phosphorus, boron, and germanium, or (b) a first layer containing the germanium and a second layer containing the silicon.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: August 27, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Shinji Mori, Masayuki Tanaka, Kazuhiro Matsuo, Kenichiro Toratani, Keiichi Sawa, Kazuhisa Matsuda, Atsushi Takahashi, Yuta Saito
  • Patent number: 10312255
    Abstract: According to one embodiment, the plurality of charge storage films are separated in a stacking direction with a second air gap interposed. The plurality of insulating films are provided on side surfaces of electrode layers opposing the charge storage films, on portions of surfaces of the electrode layers continuous from the side surfaces and opposing a first air gap between the electrode layers, and on corners of the electrode layers between the portions and the side surfaces. The plurality of insulating films are divided in the stacking direction with a third air gap interposed and without the charge storage films being interposed. The third air gap communicates with the first air gap and the second air gap between the first air gap and the second air gap.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: June 4, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuhito Yoshimizu, Satoshi Wakatsuki, Yohei Sato, Keiichi Sawa