Patents by Inventor Keiichi SAWA

Keiichi SAWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10283646
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes first and second gate electrode layers, an inter-layer insulating layer, a channel layer, a tunneling insulating layer, first and second charge storage portions, and a blocking insulating layer. The channel layer is separated from the first and second gate electrode layers, and the inter-layer insulating layer. The tunneling insulating layer is provided between the first gate electrode layer and the channel layer. The first charge storage portion is provided between the first gate electrode layer and the tunneling insulating layer. The second charge storage portion is provided the second gate electrode layer and the tunneling insulating layer. The blocking insulating layer is provided between the inter-layer insulating layer and the tunneling insulating layer, between the first gate electrode layer and the first charge storage portion, between the inter-layer insulating layer and the first charge storage portion.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: May 7, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Keiichi Sawa, Shinji Mori, Masayuki Tanaka, Kenichiro Toratani, Takashi Furuhashi
  • Publication number: 20190027538
    Abstract: In one embodiment, a semiconductor storage device includes a first interconnect extending in a first direction, a plurality of second interconnects extending in a second direction different from the first direction, and a plurality of first insulators provided alternately with the second interconnects. The device further includes a resistance change film provided between the first interconnect and at least one of the second interconnects and including a first metal layer or a first semiconductor layer that includes a first face provided on a first interconnect side and a second face provided on a second interconnect side, at least any of the first face and the second face having a curved plane shape.
    Type: Application
    Filed: February 8, 2018
    Publication date: January 24, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Keiichi Sawa, Kazuhisa Matsuda, Atsushi Takahashi, Takaumi Morita, Masayuki Tanaka, Shinji Mori, Kazuhiro Matsuo, Yuta Saito, Kenichiro Toratani, Hisashi Okuchi
  • Publication number: 20180277757
    Abstract: A semiconductor memory device includes a plurality of first interconnections extending in a first direction, and a second interconnection extending in a second direction different from the first direction. The device further includes a resistance change film provided between the plurality of first interconnections and the second interconnection, the resistance change film including(a) silicon and a semiconductor layer including one or more elements selected from among oxygen, carbon, nitrogen, phosphorus, boron, and germanium, or (b) a first layer containing the germanium and a second layer containing the silicon.
    Type: Application
    Filed: September 5, 2017
    Publication date: September 27, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Shinji MORI, Masayuki TANAKA, Kazuhiro MATSUO, Kenichiro TORATANI, Keiichi SAWA, Kazuhisa MATSUDA, Atsushi TAKAHASHI, Yuta SAITO
  • Publication number: 20180240806
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of U-shaped memory strings, each of the plurality of U-shaped memory strings including a first columnar body, a second columnar body, and a conductive connection body. The conductive connection body connects the first columnar body and the second columnar body. A plurality of first memory cells are connected in series in the first columnar body and are composed of a plurality of first conductive layers, a first inter-gate insulating film, a plurality of first floating electrodes, a first tunnel insulating film, and a first memory channel layer. The plurality of first floating electrodes are separated from the plurality of first conductive layers by the first inter-gate insulating film. A plurality of second memory cells are connected in series in the second columnar body, similarly to the plurality of first memory cells.
    Type: Application
    Filed: April 19, 2018
    Publication date: August 23, 2018
    Applicant: Toshiba Memory Corporation
    Inventor: Keiichi SAWA
  • Patent number: 9997533
    Abstract: According to one embodiment, the plurality of charge storage films are separated in a stacking direction with a second air gap interposed. The plurality of insulating films are provided on side surfaces of electrode layers opposing the charge storage films, on portions of surfaces of the electrode layers continuous from the side surfaces and opposing a first air gap between the electrode layers, and on corners of the electrode layers between the portions and the side surfaces. The plurality of insulating films are divided in the stacking direction with a third air gap interposed and without the charge storage films being interposed. The third air gap communicates with the first air gap and the second air gap between the first air gap and the second air gap.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: June 12, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuhito Yoshimizu, Satoshi Wakatsuki, Yohei Sato, Keiichi Sawa
  • Patent number: 9978765
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of U-shaped memory strings, each of the plurality of U-shaped memory strings including a first columnar body, a second columnar body, and a conductive connection body. The conductive connection body connects the first columnar body and the second columnar body. A plurality of first memory cells are connected in series in the first columnar body and are composed of a plurality of first conductive layers, a first inter-gate insulating film, a plurality of first floating electrodes, a first tunnel insulating film, and a first memory channel layer. The plurality of first floating electrodes are separated from the plurality of first conductive layers by the first inter-gate insulating film. A plurality of second memory cells are connected in series in the second columnar body, similarly to the plurality of first memory cells.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: May 22, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Keiichi Sawa
  • Publication number: 20180053781
    Abstract: According to one embodiment, the plurality of charge storage films are separated in a stacking direction with a second air gap interposed. The plurality of insulating films are provided on side surfaces of electrode layers opposing the charge storage films, on portions of surfaces of the electrode layers continuous from the side surfaces and opposing a first air gap between the electrode layers, and on corners of the electrode layers between the portions and the side surfaces. The plurality of insulating films are divided in the stacking direction with a third air gap interposed and without the charge storage films being interposed. The third air gap communicates with the first air gap and the second air gap between the first air gap and the second air gap.
    Type: Application
    Filed: November 1, 2017
    Publication date: February 22, 2018
    Inventors: Yasuhito Yoshimizu, Satoshi Wakatsuki, Yohei Sato, Keiichi Sawa
  • Patent number: 9892930
    Abstract: A semiconductor memory device includes a first electrode layer; a second electrode layer provided above the first electrode layer; a first insulating oxide layer provided between the first and second electrode layers; a semiconductor layer extending through the first electrode layer, the first insulating oxide layer and the second electrode layer that are stacked in the first direction; and a second insulating oxide layer extending in the first direction between the semiconductor layer and the first insulating oxide layer, the second insulating oxide layer being in contact with the first insulating oxide layer. At least one of the first insulating oxide layer and the second insulating oxide layer includes nitrogen atoms. The nitrogen atoms are distributed around an interface between the first insulating oxide layer and the second insulating oxide layer, or distributed in the vicinity of the interface.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: February 13, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Keiichi Sawa, Shinji Mori, Masayuki Tanaka, Katsuyuki Kitamoto
  • Publication number: 20170263780
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes first and second gate electrode layers, an inter-layer insulating layer, a channel layer, a tunneling insulating layer, first and second charge storage portions, and a blocking insulating layer. The channel layer is separated from the first and second gate electrode layers, and the inter-layer insulating layer. The tunneling insulating layer is provided between the first gate electrode layer and the channel layer. The first charge storage portion is provided between the first gate electrode layer and the tunneling insulating layer. The second charge storage portion is provided the second gate electrode layer and the tunneling insulating layer. The blocking insulating layer is provided between the inter-layer insulating layer and the tunneling insulating layer, between the first gate electrode layer and the first charge storage portion, between the inter-layer insulating layer and the first charge storage portion.
    Type: Application
    Filed: March 9, 2017
    Publication date: September 14, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keiichi SAWA, Shinji MORI, Masayuki Tanaka, Kenichiro Tortani, Takashi Furuhashi
  • Publication number: 20170098659
    Abstract: According to one embodiment, the plurality of charge storage films are separated in a stacking direction with a second air gap interposed. The plurality of insulating films are provided on side surfaces of electrode layers opposing the charge storage films, on portions of surfaces of the electrode layers continuous from the side surfaces and opposing a first air gap between the electrode layers, and on corners of the electrode layers between the portions and the side surfaces. The plurality of insulating films are divided in the stacking direction with a third air gap interposed and without the charge storage films being interposed. The third air gap communicates with the first air gap and the second air gap between the first air gap and the second air gap.
    Type: Application
    Filed: March 15, 2016
    Publication date: April 6, 2017
    Inventors: Yasuhito YOSHIMIZU, Satoshi WAKATSUKI, Yohei SATO, Keiichi SAWA
  • Publication number: 20170040340
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body; a semiconductor body; and charge storage film. The stacked body includes the plurality of electrode layers separately stacked each other. The semiconductor body is provided in the stacked body and extends in a stack direction of the stacked body and includes an oxide semiconductor. The charge storage film is provided between the semiconductor body and the plurality of electrode layers.
    Type: Application
    Filed: October 20, 2016
    Publication date: February 9, 2017
    Inventors: Katsuaki NATORI, Masayuki TANAKA, Keiichi SAWA, Tetsuya KAI, Shinji MORI
  • Publication number: 20160343657
    Abstract: According to one embodiment, a semiconductor device includes a stacked body, a core film, and a stacked film. The stacked body includes a plurality of conductive layers stacked with an insulating layer between the conductive layers. The core film extends in the stacked body in a stacking direction of the stacked body, and includes a metal oxide film having a higher dielectric constant than a dielectric constant of silicon nitride. The stacked film includes a semiconductor film and charge storage film. The semiconductor film is provided between the conductive layers and the core film. The semiconductor film extends in the stacking direction. The charge storage film is provided between the conductive layers and the semiconductor film.
    Type: Application
    Filed: August 17, 2015
    Publication date: November 24, 2016
    Inventors: Keiichi SAWA, Masayuki TANAKA
  • Publication number: 20160155749
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of U-shaped memory strings, each of the plurality of U-shaped memory strings including a first columnar body, a second columnar body, and a conductive connection body. The conductive connection body connects the first columnar body and the second columnar body. A plurality of first memory cells are connected in series in the first columnar body and are composed of a plurality of first conductive layers, a first inter-gate insulating film, a plurality of first floating electrodes, a first tunnel insulating film, and a first memory channel layer. The plurality of first floating electrodes are separated from the plurality of first conductive layers by the first inter-gate insulating film. A plurality of second memory cells are connected in series in the second columnar body, similarly to the plurality of first memory cells.
    Type: Application
    Filed: February 3, 2016
    Publication date: June 2, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Keiichi SAWA
  • Patent number: 9312271
    Abstract: According to an embodiment, a non-volatile memory device includes electrodes, an inter-layer insulating film between the electrodes and at least one semiconductor layer extending through the electrodes and the inter-layer insulating film. The device includes a charge storage layer between the semiconductor layer and each electrode, a first insulating film between the charge storage layer and the semiconductor layer, and a second insulating film. The second insulating film includes a first portion between the charge storage layer and each electrode, a second portion between each electrode and the inter-layer insulating film, and a third portion that links the first portion and the second portion. In a cross-section of the third portion parallel to the first direction and a second direction toward each electrode from the charge storage layer, a curved surface on the charge storage layer side has a curvature radius larger than a surface on the electrodes side.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: April 12, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keiichi Sawa, Masayuki Tanaka, Katsuaki Natori
  • Patent number: 9287388
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of U-shaped memory strings, each of the plurality of U-shaped memory strings including a first columnar body, a second columnar body, and a conductive connection body. The conductive connection body connects the first columnar body and the second columnar body. A plurality of first memory cells are connected in series in the first columnar body and are composed of a plurality of first conductive layers, a first inter-gate insulating film, a plurality of first floating electrodes, a first tunnel insulating film, and a first memory channel layer. The plurality of first floating electrodes are separated from the plurality of first conductive layers by the first inter-gate insulating film. A plurality of second memory cells are connected in series in the second columnar body, similally to the plurality of first memory cells.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: March 15, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Keiichi Sawa
  • Publication number: 20160064406
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body; a semiconductor body; and charge storage film. The stacked body includes the plurality of electrode layers separately stacked each other. The semiconductor body is provided in the stacked body and extends in a stack direction of the stacked body and includes an oxide semiconductor. The charge storage film is provided between the semiconductor body and the plurality of electrode layers.
    Type: Application
    Filed: February 4, 2015
    Publication date: March 3, 2016
    Inventors: Katsuaki NATORI, Masayuki Tanaka, Keiichi Sawa, Tetsuya Kai, Shinji Mori
  • Publication number: 20160035740
    Abstract: According to an embodiment, a non-volatile memory device includes electrodes, an inter-layer insulating film between the electrodes and at least one semiconductor layer extending through the electrodes and the inter-layer insulating film. The device includes a charge storage layer between the semiconductor layer and each electrode, a first insulating film between the charge storage layer and the semiconductor layer, and a second insulating film. The second insulating film includes a first portion between the charge storage layer and each electrode, a second portion between each electrode and the inter-layer insulating film, and a third portion that links the first portion and the second portion. In a cross-section of the third portion parallel to the first direction and a second direction toward each electrode from the charge storage layer, a curved surface on the charge storage layer side has a curvature radius larger than a surface on the electrodes side.
    Type: Application
    Filed: January 15, 2015
    Publication date: February 4, 2016
    Inventors: Keiichi SAWA, Masayuki TANAKA, Katsuaki NATORI
  • Patent number: 9082703
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: a semiconductor layer; a first insulating film provided on the semiconductor layer; a floating gate layer provided on the first insulating film; a second insulating film provided on the floating gate layer; and a gate electrode provided on the second insulating film, the first insulating film including silicon, oxygen, and carbon. Concentration of the carbon in a direction from the semiconductor layer side toward the floating gate layer side has a maximum between the semiconductor layer and the floating gate layer, and the maximum being located nearer to the semiconductor layer side than to the floating gate layer side.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: July 14, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Murakoshi, Keiichi Sawa
  • Publication number: 20150069493
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: a semiconductor layer; a first insulating film provided on the semiconductor layer; a floating gate layer provided on the first insulating film; a second insulating film provided on the floating gate layer; and a gate electrode provided on the second insulating film, the first insulating film including silicon, oxygen, and carbon. Concentration of the carbon in a direction from the semiconductor layer side toward the floating gate layer side has a maximum between the semiconductor layer and the floating gate layer, and the maximum being located nearer to the semiconductor layer side than to the floating gate layer side.
    Type: Application
    Filed: January 29, 2014
    Publication date: March 12, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Atsushi MURAKOSHI, Keiichi Sawa
  • Publication number: 20130264626
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of U-shaped memory strings, each of the plurality of U-shaped memory strings including a first columnar body, a second columnar body, and a conductive connection body. The conductive connection body connects the first columnar body and the second columnar body. A plurality of first memory cells are connected in series in the first columnar body and are composed of a plurality of first conductive layers, a first inter-gate insulating film, a plurality of first floating electrodes, a first tunnel insulating film, and a first memory channel layer. The plurality of first floating electrodes are separated from the plurality of first conductive layers by the first inter-gate insulating film. A plurality of second memory cells are connected in series in the second columnar body, similally to the plurality of first memory cells.
    Type: Application
    Filed: February 28, 2013
    Publication date: October 10, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Keiichi SAWA