Patents by Inventor Keiji Okumura

Keiji Okumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11984498
    Abstract: A semiconductor device includes a current spreading region of the first conductivity type provided on a drift layer and having a higher impurity density than the drift layer; a base region of a second conductivity type provided on the current spreading region; a base contact region of the second conductivity type provided in a top part of the base region and having a higher impurity density than the base region; and an electrode contact region of the first conductivity type provided in a top part of the base region that is laterally in contact with the base contact region, the electrode contact region having a higher impurity density than the drift layer, wherein a density of a second conductivity type impurity element in the base contact region is at least two times as much as a density of a first conductivity type impurity element in the electrode contact region.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: May 14, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura
  • Publication number: 20240145589
    Abstract: A semiconductor device having an active portion and a gate pad portion on a semiconductor substrate includes: a first semiconductor layer of a first conductivity type; and a second semiconductor layer of a second conductivity type. The active portion has: first semiconductor regions of the first conductivity type; a first electrode provided on the first semiconductor regions; and first trenches. The gate pad portion has: a gate electrode pad provided above the second semiconductor layer; second trenches provided beneath the gate electrode pad; and second semiconductor regions of the second conductivity type, each provided in the first semiconductor layer so as to be in contact with a respective one of bottoms of the second trenches. Each of the second trenches is continuous with a respective one of the first trenches. The second semiconductor layer is continuous from the active portion to the gate pad portion.
    Type: Application
    Filed: January 10, 2024
    Publication date: May 2, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji OKUMURA
  • Publication number: 20240120322
    Abstract: A semiconductor device includes a MOSFET including a PN junction diode. A unipolar device is connected in parallel to the MOSFET and has two terminals. A first wire connects the PN junction diode to one of the two terminals of the unipolar device. A second wire connects the one of the two terminals of the unipolar device to an output line, so that the output line is connected to the MOSFET and the unipolar device via the first wire and the second wire. In one embodiment the connection of the first wire to the diode is with its anode, and in another the connection is with the cathode.
    Type: Application
    Filed: December 19, 2023
    Publication date: April 11, 2024
    Applicant: ROHM CO., LTD.
    Inventor: Keiji OKUMURA
  • Patent number: 11908929
    Abstract: A semiconductor device having an active portion and a gate pad portion on a semiconductor substrate includes: a first semiconductor layer of a first conductivity type; and a second semiconductor layer of a second conductivity type. The active portion has: first semiconductor regions of the first conductivity type; a first electrode provided on the first semiconductor regions; and first trenches. The gate pad portion has: a gate electrode pad provided above the second semiconductor layer; second trenches provided beneath the gate electrode pad; and second semiconductor regions of the second conductivity type, each provided in the first semiconductor layer so as to be in contact with a respective one of bottoms of the second trenches. Each of the second trenches is continuous with a respective one of the first trenches. The second semiconductor layer is continuous from the active portion to the gate pad portion.
    Type: Grant
    Filed: October 26, 2022
    Date of Patent: February 20, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura
  • Patent number: 11894349
    Abstract: A semiconductor device includes a MOSFET including a PN junction diode. A unipolar device is connected in parallel to the MOSFET and has two terminals. A first wire connects the PN junction diode to one of the two terminals of the unipolar device. A second wire connects the one of the two terminals of the unipolar device to an output line, so that the output line is connected to the MOSFET and the unipolar device via the first wire and the second wire. In one embodiment the connection of the first wire to the diode is with its anode, and in another the connection is with the cathode.
    Type: Grant
    Filed: October 4, 2022
    Date of Patent: February 6, 2024
    Assignee: ROHM CO., LTD.
    Inventor: Keiji Okumura
  • Publication number: 20240014270
    Abstract: An insulated-gate semiconductor device, which has trenches arranged in a chip structure, the trenches defining both sidewalls in a first and second sidewall surface facing each other, includes: a first unit cell including a main-electrode region in contact with a first sidewall surface of a first trench, a base region in contact with a bottom surface of the main-electrode region and the first sidewall surface, a drift layer in contact with a bottom surface of the base region and the first sidewall surface, and a gate protection-region in contact with the second sidewall surface and a bottom surface of the first trench; and a second unit cell including an operation suppression region in contact with a first sidewall surface and a second sidewall surface of a second trench, wherein the second unit cell includes the second trench located at one end of an array of the trenches.
    Type: Application
    Filed: September 20, 2023
    Publication date: January 11, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji OKUMURA
  • Patent number: 11798993
    Abstract: An insulated-gate semiconductor device, which has trenches arranged in a chip structure, the trenches defining both sidewalls in a first and second sidewall surface facing each other, includes: a first unit cell including a main-electrode region in contact with a first sidewall surface of a first trench, a base region in contact with a bottom surface of the main-electrode region and the first sidewall surface, a drift layer in contact with a bottom surface of the base region and the first sidewall surface, and a gate protection-region in contact with the second sidewall surface and a bottom surface of the first trench; and a second unit cell including an operation suppression region in contact with a first sidewall surface and a second sidewall surface of a second trench, wherein the second unit cell includes the second trench located at one end of an array of the trenches.
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: October 24, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura
  • Patent number: 11695045
    Abstract: In a silicon carbide semiconductor device and a silicon carbide semiconductor circuit device equipped with the silicon carbide semiconductor device, a gate leak current that flows when negative voltage with respect to the potential of a source electrode is applied to the gate electrode is limited to less than 2×10?11 A and the gate leak current is limited to less than 3.7×10?6 A/m2.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: July 4, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Keiji Okumura, Akimasa Kinoshita
  • Publication number: 20230154986
    Abstract: An insulated-gate semiconductor device, which has trenches arranged in a chip structure, the trenches defining both sidewalls in a first and second sidewall surface facing each other, includes: a first unit cell including a main-electrode region in contact with a first sidewall surface of a first trench, a base region in contact with a bottom surface of the main-electrode region and the first sidewall surface, a drift layer in contact with a bottom surface of the base region and the first sidewall surface, and a gate protection-region in contact with the second sidewall surface and a bottom surface of the first trench; and a second unit cell including an operation suppression region in contact with a first sidewall surface and a second sidewall surface of a second trench, wherein the second unit cell includes the second trench located at one end of an array of the trenches.
    Type: Application
    Filed: January 17, 2023
    Publication date: May 18, 2023
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji OKUMURA
  • Patent number: 11637199
    Abstract: A semiconductor device, including a first semiconductor layer of the first conductivity type formed on a semiconductor substrate, a first semiconductor region of the first conductivity type, a first base region and a first base region, both of a second conductivity type, selectively provided in the first semiconductor layer, a second semiconductor layer of the second conductivity type provided on the first semiconductor layer, a second semiconductor region of the first conductivity type selectively provided in the second semiconductor layer, a trench penetrating the second semiconductor layer and the second semiconductor region, a gate electrode provided in the trench, an interlayer insulating film provided on the gate electrode, a second base region in contact with a bottom of the trench, a first electrode in contact with the second semiconductor layer and the second semiconductor region, and a second electrode provided on the back of the semiconductor substrate.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: April 25, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura
  • Patent number: 11631668
    Abstract: An electronic circuit having a first terminal and a second terminal. The electronic circuit includes a plurality of diodes connected in parallel, the plurality of diodes including a first diode and a second diode that respectively have applied thereto a first forward voltage and a second forward voltage, the second forward voltage being higher than the first forward voltage. A first path and a second path are formed from the first terminal, respectively via the first diode and the second diode, to the second terminal. An inductance of the first path is larger than an inductance of the second path.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: April 18, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura
  • Patent number: 11610969
    Abstract: An insulated-gate semiconductor device, which has trenches arranged in a chip structure, the trenches defining both sidewalls in a first and second sidewall surface facing each other, includes: a first unit cell including a main-electrode region in contact with a first sidewall surface of a first trench, a base region in contact with a bottom surface of the main-electrode region and the first sidewall surface, a drift layer in contact with a bottom surface of the base region and the first sidewall surface, and a gate protection-region in contact with the second sidewall surface and a bottom surface of the first trench; and a second unit cell including an operation suppression region in contact with a first sidewall surface and a second sidewall surface of a second trench, wherein the second unit cell includes the second trench located at one end of an array of the trenches.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: March 21, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura
  • Publication number: 20230049039
    Abstract: A semiconductor device having an active portion and a gate pad portion on a semiconductor substrate includes: a first semiconductor layer of a first conductivity type; and a second semiconductor layer of a second conductivity type. The active portion has: first semiconductor regions of the first conductivity type; a first electrode provided on the first semiconductor regions; and first trenches. The gate pad portion has: a gate electrode pad provided above the second semiconductor layer; second trenches provided beneath the gate electrode pad; and second semiconductor regions of the second conductivity type, each provided in the first semiconductor layer so as to be in contact with a respective one of bottoms of the second trenches. Each of the second trenches is continuous with a respective one of the first trenches. The second semiconductor layer is continuous from the active portion to the gate pad portion.
    Type: Application
    Filed: October 26, 2022
    Publication date: February 16, 2023
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji OKUMURA
  • Publication number: 20230025045
    Abstract: A semiconductor device includes a MOSFET including a PN junction diode. A unipolar device is connected in parallel to the MOSFET and has two terminals. A first wire connects the PN junction diode to one of the two terminals of the unipolar device. A second wire connects the one of the two terminals of the unipolar device to an output line, so that the output line is connected to the MOSFET and the unipolar device via the first wire and the second wire. In one embodiment the connection of the first wire to the diode is with its anode, and in another the connection is with the cathode.
    Type: Application
    Filed: October 4, 2022
    Publication date: January 26, 2023
    Inventor: Keiji OKUMURA
  • Publication number: 20220367294
    Abstract: A method of manufacturing a silicon carbide semiconductor device. The method includes providing a starting substrate containing silicon carbide, epitaxially growing an epitaxial layer on the starting substrate to thereby form a semiconductor wafer, forming a plurality of scribe lines at a surface of the semiconductor wafer to delineate a plurality of chip regions, forming a mark in the epitaxial layer, the mark being formed in a marking region that is outside the scribe lines, inspecting the epitaxial layer for a crystal defect, forming a device element structure in at least one of the plurality of chip regions, dicing the semiconductor wafer into a plurality of individual semiconductor chips along the plurality of scribe lines, and identifying, as a conforming product candidate, one of the plurality of semiconductor chips that is free of the crystal defect detected during the inspecting.
    Type: Application
    Filed: March 25, 2022
    Publication date: November 17, 2022
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Hidetatsu NAKAMURA, Keiji OKUMURA, Yoshikuni FUJIMOTO
  • Publication number: 20220367274
    Abstract: A method of manufacturing a silicon carbide semiconductor device. The method includes epitaxially growing an epitaxial layer on a starting substrate to form a semiconductor wafer, forming a plurality of scribe lines, including a first scribe line, in the epitaxial layer, forming a mark in the first scribe line, inspecting the epitaxial layer for a crystal defect using crystal defect inspection equipment, which recognizes the first scribe line as being a second scribe line, forming a device element structure in the semiconductor wafer, dicing the semiconductor wafer into semiconductor chips along the scribe lines, and identifying, as a conforming product candidate, one of the semiconductor chips that is free of the crystal defect detected during the inspecting. A distance between an edge of the second scribe line and an edge of the mark, when the first and second scribe lines are aligned, is in a range from 10 ?m to 25 ?m.
    Type: Application
    Filed: March 29, 2022
    Publication date: November 17, 2022
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Hidetatsu NAKAMURA, Keiji OKUMURA, Yoshikuni FUJIMOTO
  • Patent number: 11502063
    Abstract: A semiconductor device includes a MOSFET including a PN junction diode. A unipolar device is connected in parallel to the MOSFET and has two terminals. A first wire connects the PN junction diode to one of the two terminals of the unipolar device. A second wire connects the one of the two terminals of the unipolar device to an output line, so that the output line is connected to the MOSFET and the unipolar device via the first wire and the second wire. In one embodiment the connection of the first wire to the diode is with its anode, and in another the connection is with the cathode.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: November 15, 2022
    Assignee: ROHM CO., LTD.
    Inventor: Keiji Okumura
  • Patent number: 11489071
    Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, having an active portion and a gate pad portion; a first semiconductor layer of the first conductivity type; and a second semiconductor layer of a second conductivity type. The active portion has first semiconductor regions of the first conductivity type, first trenches, gate insulating films, first gate electrodes, an interlayer insulating film, and second semiconductor regions of the second conductivity type. The gate pad portion has at least one second trench, an insulating film 9b, at least one second gate electrode, at least one fourth semiconductor region of the second conductivity type, and a gate electrode pad. Between the gate electrode pad and the semiconductor substrate, a polycrystalline silicon film is provided.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: November 1, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura
  • Patent number: 11430714
    Abstract: In an inactive region of an active region, a gate pad, a gate poly-silicon layer, and a gate finger are provided at a front surface of a semiconductor substrate, via an insulating film. The gate poly-silicon layer is provided beneath the gate pad, sandwiching the insulating film therebetween. The gate pad, the gate poly-silicon layer, a gate finger, gate electrodes of a trench gate structure, a gate finger, and a second measurement pad are electrically connected in the order stated. As a result, the gate electrodes where parasitic resistance occurs and the gate poly-silicon layer where built-in resistance occurs are connected in series between the second measurement pad and the gate pad. A resistance value of the overall gate resistance that is a combined resistance of the built-in resistance and the parasitic resistance may be measured by the second measurement pad.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: August 30, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura
  • Patent number: 11410892
    Abstract: A portion of a source electrode exposed by an opening in a passivation film is used as a portion of a source pad. A first portion of the source pad includes a plating film formed by a material that is harder than a material of the source electrode. During screening, a probe needle that is a metal contact contacts the plating film that is on the first portion of the source pad. A second portion of the source pad has a layer structure different from that of the first portion of the source pad and in a second direction parallel to the front surface of the semiconductor chip, is disposed adjacently to and electrically connected to the first portion of the source pad. A bonding wire is wire bonded to the second portion of the source pad after an inspection process of the semiconductor chip.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: August 9, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura