Patents by Inventor Keiji Okumura

Keiji Okumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210104500
    Abstract: A semiconductor device includes a MOSFET including a PN junction diode. A unipolar device is connected in parallel to the MOSFET and has two terminals. A first wire connects the PN junction diode to one of the two terminals of the unipolar device. A second wire connects the one of the two terminals of the unipolar device to an output line, so that the output line is connected to the MOSFET and the unipolar device via the first wire and the second wire. In one embodiment the connection of the first wire to the diode is with its anode, and in another the connection is with the cathode.
    Type: Application
    Filed: December 17, 2020
    Publication date: April 8, 2021
    Inventor: Keiji OKUMURA
  • Publication number: 20210031660
    Abstract: An armrest includes a cable to be connected to a seat-side cable arranged on a seat, and a body member that is mountable on the seat and includes a routing section therein in which the cable is arranged. The cable includes an arranged portion that is arranged in the routing section and a connecting operation section that extends outside the routing section when being connected to the seat-side cable. The connecting operation section is arranged in the routing section when the body member is mounted on the seat.
    Type: Application
    Filed: January 24, 2019
    Publication date: February 4, 2021
    Applicants: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO RIKO COMPANY LIMITED, TOKAI CHEMICAL INDUSTRIES, LTD.
    Inventors: Satoshi YAMAMOTO, Makoto HIGASHIKOZONO, Kaho HAYASHI, Hideki OSHIMA, Takahiko ENDO, Keiji MAKINO, Jun JIN, Takemasa OKUMURA
  • Publication number: 20210030157
    Abstract: An armrest according to the technology described herein includes a bracket, an armrest body, a device connecting port, an armrest-side connector, and a cable. The bracket is fixed to a seat frame. The armrest body is attached to the bracket to be rotatable. The device connecting port is exposed through an outer surface of the armrest body. The armrest-side connector is fixed to the seat frame at a position different from the bracket. The cable includes an end connected to the device connecting port and an end connected to an armrest-side connector. The armrest body includes a cable retaining portion through which the cable is passed and in which the cable is retained. Any one of the bracket and the armrest body includes a hole (an elongated hole) that allows movement of the cable along with rotation of the armrest body.
    Type: Application
    Filed: January 23, 2019
    Publication date: February 4, 2021
    Applicants: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO RIKO COMPANY LIMITED, TOKAI CHEMICAL INDUSTRIES, LTD.
    Inventors: Satoshi YAMAMOTO, Makoto HIGASHIKOZONO, Kaho HAYASHI, Hideki OSHIMA, Takahiko ENDO, Keiji MAKINO, Jun JIN, Takemasa OKUMURA
  • Publication number: 20210020751
    Abstract: In a silicon carbide semiconductor device and a silicon carbide semiconductor circuit device equipped with the silicon carbide semiconductor device, a gate leak current that flows when negative voltage with respect to the potential of a source electrode is applied to the gate electrode is limited to less than 2×10?11 A and the gate leak current is limited to less than 3.7×10?6 A/m2.
    Type: Application
    Filed: October 1, 2020
    Publication date: January 21, 2021
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Keiji OKUMURA, Akimasa KINOSHITA
  • Patent number: 10896896
    Abstract: A semiconductor device includes a MOSFET including a PN junction diode. A unipolar device is connected in parallel to the MOSFET and has two terminals. A first wire connects the PN junction diode to one of the two terminals of the unipolar device. A second wire connects the one of the two terminals of the unipolar device to an output line, so that the output line is connected to the MOSFET and the unipolar device via the first wire and the second wire. In one embodiment the connection of the first wire to the diode is with its anode, and in another the connection is with the cathode.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: January 19, 2021
    Assignee: ROHM CO., LTD.
    Inventor: Keiji Okumura
  • Publication number: 20210013339
    Abstract: A semiconductor device includes a current spreading region of the first conductivity type provided on a drift layer and having a higher impurity density than the drift layer; a base region of a second conductivity type provided on the current spreading region; a base contact region of the second conductivity type provided in a top part of the base region and having a higher impurity density than the base region; and an electrode contact region of the first conductivity type provided in a top part of the base region that is laterally in contact with the base contact region, the electrode contact region having a higher impurity density than the drift layer, wherein a density of a second conductivity type impurity element in the base contact region is at least two times as much as a density of a first conductivity type impurity element in the electrode contact region.
    Type: Application
    Filed: September 29, 2020
    Publication date: January 14, 2021
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji OKUMURA
  • Publication number: 20210013128
    Abstract: In an inactive region of an active region, a gate pad, a gate poly-silicon layer, and a gate finger are provided at a front surface of a semiconductor substrate, via an insulating film. The gate poly-silicon layer is provided beneath the gate pad, sandwiching the insulating film therebetween. The gate pad, the gate poly-silicon layer, a gate finger, gate electrodes of a trench gate structure, a gate finger, and a second measurement pad are electrically connected in the order stated. As a result, the gate electrodes where parasitic resistance occurs and the gate poly-silicon layer where built-in resistance occurs are connected in series between the second measurement pad and the gate pad. A resistance value of the overall gate resistance that is a combined resistance of the built-in resistance and the parasitic resistance may be measured by the second measurement pad.
    Type: Application
    Filed: September 28, 2020
    Publication date: January 14, 2021
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji OKUMURA
  • Patent number: 10840369
    Abstract: A semiconductor device includes a current spreading region of the first conductivity type provided on a drift layer and having a higher impurity density than the drift layer; a base region of a second conductivity type provided on the current spreading region; a base contact region of the second conductivity type provided in a top part of the base region and having a higher impurity density than the base region; and an electrode contact region of the first conductivity type provided in a top part of the base region that is laterally in contact with the base contact region, the electrode contact region having a higher impurity density than the drift layer, wherein a density of a second conductivity type impurity element in the base contact region is at least two times as much as a density of a first conductivity type impurity element in the electrode contact region.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: November 17, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura
  • Patent number: 10840340
    Abstract: In a MOS silicon carbide semiconductor device and a silicon carbide semiconductor circuit device equipped with the silicon carbide semiconductor device, a gate leak current that flows when negative voltage with respect to the potential of the source electrode is applied to the gate electrode is limited to less than 2×10?11 A. The negative voltage applied to the gate electrode is limited to ?3V or lower relative to the potential of the source electrode.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: November 17, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Keiji Okumura, Akimasa Kinoshita
  • Patent number: 10833189
    Abstract: In an inactive region of an active region, a gate pad, a gate poly-silicon layer, and a gate finger are provided at a front surface of a semiconductor substrate, via an insulating film. The gate poly-silicon layer is provided beneath the gate pad, sandwiching the insulating film therebetween. The gate pad, the gate poly-silicon layer, a gate finger, gate electrodes of a trench gate structure, a gate finger, and a second measurement pad are electrically connected in the order stated. As a result, the gate electrodes where parasitic resistance occurs and the gate poly-silicon layer where built-in resistance occurs are connected in series between the second measurement pad and the gate pad. A resistance value of the overall gate resistance that is a combined resistance of the built-in resistance and the parasitic resistance may be measured by the second measurement pad.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: November 10, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura
  • Publication number: 20200321451
    Abstract: A method for producing a semiconductor power device, includes forming a gate trench from a surface of a semiconductor layer toward an inside thereof. A first insulation film is formed on an inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.
    Type: Application
    Filed: June 18, 2020
    Publication date: October 8, 2020
    Inventors: Keiji OKUMURA, Mineo MIURA, Yuki NAKANO, Noriaki KAWAMOTO, Hidetoshi ABE
  • Publication number: 20200307655
    Abstract: A rubbing plate of a side bearer of a railcar bogie is a rubbing plate of a side bearer provided at the railcar bogie so as to slidably contact a slide member arranged above or under the side bearer. The rubbing plate includes a recess-projection provided on an opposing surface of the rubbing plate, the opposing surface being opposed to a sliding surface of the slide member.
    Type: Application
    Filed: March 30, 2020
    Publication date: October 1, 2020
    Applicants: KAWASAKI JUKOGYO KABUSHIKI KAISHA, STARLITE Co., Ltd.
    Inventors: Yasufumi OKUMURA, Yoshi SATO, Keiji TADA, Noriaki SHIBITA
  • Publication number: 20200303269
    Abstract: A portion of a source electrode exposed by an opening in a passivation film is used as a portion of a source pad. A first portion of the source pad includes a plating film formed by a material that is harder than a material of the source electrode. During screening, a probe needle that is a metal contact contacts the plating film that is on the first portion of the source pad. A second portion of the source pad has a layer structure different from that of the first portion of the source pad and in a second direction parallel to the front surface of the semiconductor chip, is disposed adjacently to and electrically connected to the first portion of the source pad. A bonding wire is wire bonded to the second portion of the source pad after an inspection process of the semiconductor chip.
    Type: Application
    Filed: January 27, 2020
    Publication date: September 24, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji OKUMURA
  • Publication number: 20200303541
    Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate, a first semiconductor layer and a first semiconductor region each of a first conductivity type, and a first base region, a second semiconductor layer and a second semiconductor region each of a second conductivity type. The first base region opposes the second semiconductor region in a depth direction. A distribution of point defects in a depth direction from a first surface of the second semiconductor region, opposite a second surface of the second semiconductor region facing toward a front surface of the silicon carbide semiconductor substrate has two peaks at positions deeper than an interface between the first semiconductor layer and the first base region, where a first peak at a deeper position of the two peaks has a greater quantity of the point defects than does a second peak at a shallower position of the two peaks.
    Type: Application
    Filed: March 2, 2020
    Publication date: September 24, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji OKUMURA
  • Publication number: 20200295141
    Abstract: On a front surface of a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type having an impurity concentration lower than an impurity concentration of the silicon carbide semiconductor substrate is formed. A base region of a second conductivity type is selectively formed in the first semiconductor layer. A second semiconductor layer of the second conductivity type is formed on a surface of the first semiconductor layer. A first semiconductor region of the first conductivity type is selectively formed in a surface layer of the second semiconductor layer. The base region is formed by implanting an impurity of the second conductivity type from an angle that relative to a perpendicular to the silicon carbide semiconductor substrate, is three degrees or more.
    Type: Application
    Filed: January 28, 2020
    Publication date: September 17, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji OKUMURA
  • Publication number: 20200294989
    Abstract: A gate pad is includes a first portion disposed in a gate pad region and a second portion disposed in a gate resistance region and connected to the first portion, the gate pad has a planar shape in which the second portion protrudes from the first portion. A gate polysilicon layer disposed on a front surface of a semiconductor substrate via a gate insulating film, between the semiconductor substrate and an interlayer insulating film, has a surface area at least equal to that of the gate pad and opposes an entire surface of the gate pad in a depth direction. ESD capability of a first region where the gate pad is provided is greater than ESD capability of a second region where a gate resistance is provided and is greater than ESD capability of a third region where a MOS structure of an active region is provided.
    Type: Application
    Filed: January 27, 2020
    Publication date: September 17, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji OKUMURA
  • Patent number: 10777677
    Abstract: An insulated gate semiconductor device includes p+ gate bottom protection regions embedded in a drift layer at the bottoms of trenches that goes through n+ source regions and p-type base regions, and p+ base bottom embedded regions embedded in the drift layer below the base regions. The base bottom embedded regions have trapezoidal shapes due to a channeling phenomenon, and the bottom surfaces of the base bottom embedded regions are deeper than the bottom surfaces of the gate bottom protection regions.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: September 15, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura
  • Patent number: 10777678
    Abstract: A semiconductor device includes: an active area including a drift layer of a first conductivity type; and a voltage blocking area arranged around the active area and including an field relaxation region having a second conductivity type, being provided in an upper portion of the drift layer, wherein a depth of the field relaxation region decreases toward outside, and a spatial-modulation portion is provided at an outer end of the field relaxation region.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: September 15, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura
  • Publication number: 20200266294
    Abstract: A semiconductor device, including a first semiconductor layer of the first conductivity type formed on a semiconductor substrate, a first semiconductor region of the first conductivity type, a first base region of a second conductivity type and a first base region of a second conductivity type that are respectively selectively provided in the first semiconductor layer, a second semiconductor layer of the second conductivity type provided on the first semiconductor layer, a second semiconductor region of the first conductivity type selectively provided in the second semiconductor layer, a trench that penetrates the second semiconductor layer and the second semiconductor region, a gate electrode provided in the trench via a gate insulating film, an interlayer insulating film provided on the gate electrode, a first electrode in contact with the second semiconductor layer and the second semiconductor region, and a second electrode provided on a back surface of the semiconductor substrate.
    Type: Application
    Filed: December 24, 2019
    Publication date: August 20, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji OKUMURA
  • Patent number: 10727318
    Abstract: A method for producing a semiconductor power device, includes forming a gate trench from a surface of a semiconductor layer toward an inside thereof. A first insulation film is formed on an inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: July 28, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Keiji Okumura, Mineo Miura, Yuki Nakano, Noriaki Kawamoto, Hidetoshi Abe