Patents by Inventor Keiji Okumura

Keiji Okumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10529848
    Abstract: An insulated-gate semiconductor device includes: an n-type current spreading layer provided on an n?-type drift layer; a p+-type base region provided on the current spreading layer; an n+-type source region provided in an upper portion of the base region; an insulated-gate electrode structure provided inside a trench; a p+-type gate-bottom protection-region provided in the current spreading layer so as to be in contact with a bottom of the trench; and a p+-type base-bottom buried-region buried in the current spreading layer, having a bottom surface having the same depth as a bottom surface of the gate-bottom protection-region, wherein the base-bottom buried-region is divided into a plurality of portions in a depth direction through an n-type separation layer.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: January 7, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura
  • Publication number: 20190371938
    Abstract: An insulated gate semiconductor device includes p+ gate bottom protection regions embedded in a drift layer at the bottoms of trenches that goes through n+ source regions and p-type base regions, and p+ base bottom embedded regions embedded in the drift layer below the base regions. The base bottom embedded regions have trapezoidal shapes due to a channeling phenomenon, and the bottom surfaces of the base bottom embedded regions are deeper than the bottom surfaces of the gate bottom protection regions.
    Type: Application
    Filed: August 20, 2019
    Publication date: December 5, 2019
    Applicant: Fuji Electric Co., Ltd.
    Inventor: Keiji OKUMURA
  • Patent number: 10490633
    Abstract: An insulated-gate semiconductor device, which has trenches arranged in a chip structure, the trenches defining both sidewalls in a first and second sidewall surface facing each other, includes: a first unit cell including a main-electrode region in contact with a first sidewall surface of a first trench, a base region in contact with a bottom surface of the main-electrode region and the first sidewall surface, a drift layer in contact with a bottom surface of the base region and the first sidewall surface, and a gate protection-region in contact with the second sidewall surface and a bottom surface of the first trench; and a second unit cell including an operation suppression region in contact with a first sidewall surface and a second sidewall surface of a second trench, wherein the second unit cell includes the second trench located at one end of an array of the trenches.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: November 26, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura
  • Patent number: 10483390
    Abstract: An insulated gate semiconductor device includes p+ gate bottom protection regions embedded in a drift layer at the bottoms of trenches that goes through n+ source regions and p-type base regions, and p+ base bottom embedded regions embedded in the drift layer below the base regions. The base bottom embedded regions have trapezoidal shapes due to a channeling phenomenon, and the bottom surfaces of the base bottom embedded regions are deeper than the bottom surfaces of the gate bottom protection regions.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: November 19, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura
  • Patent number: 10468509
    Abstract: A semiconductor device includes: an n-type drift region; a p-type base region above the drift region; a gate electrode disposed inside a trench above the drift region with a gate insulating film between the trench and the gate electrode; an n-type source region above the base region; a source electrode connected to the source region; an n-type drain region below the drift region; a drain electrode connected to the drain region; a p-type protective layer that is disposed inside the drift region and below the trench, the protective layer protruding beyond a trench width of the trench; and a p-type conductive path formation layer that is disposed between the protective layer and a bottom of the trench and protrudes beyond the trench width, the conductive path formation layer having protruding regions of which an impurity concentration therein is set so that an inversion layer is formed during ON.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: November 5, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura
  • Patent number: 10459190
    Abstract: An imaging apparatus includes: an imaging unit; an image clipping unit configured to clip a predetermined area from each of images; an analyzing unit configured to analyze the sequentially clipped predetermined areas and generate an analysis result indicating an identified subject; an autofocus (AF) target determination unit configured to determine an AF target in the images based on the analysis result; an AF mode determination unit configured to select and determine an optimal AF mode based on the analysis result and a determination result; a touch panel; an input detection unit; and an imaging control unit configured to repeat control of moving a position of the predetermined area, causing the analyzing unit to analyze the predetermined area of a latest image, causing the AF target determination unit to determine the AF target, and causing the AF mode determination unit to select and determine the optimal AF mode.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: October 29, 2019
    Assignee: Olympus Corporation
    Inventors: Takeshi Suzuki, Keiji Kunishige, Akira Yukitake, Takeshi Kawawa, Yoichiro Okumura
  • Patent number: 10428273
    Abstract: Shown are a liquid crystal compound satisfying at least one of physical properties such as high stability to heat and light, a high clearing point (or high maximum temperature), low minimum temperature of a liquid crystal phase, small viscosity, suitable optical anisotropy, large negative dielectric anisotropy, a suitable elastic constant and satisfactory compatibility with other liquid crystal compounds, a liquid crystal composition containing the compound and a liquid crystal display device including the composition.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: October 1, 2019
    Assignees: JNC CORPORATION, JNC PETROCHEMICAL CORPORATION
    Inventors: Kazuo Okumura, Tokifumi Masukawa, Keiji Kimura
  • Publication number: 20190288073
    Abstract: In a MOS silicon carbide semiconductor device and a silicon carbide semiconductor circuit device equipped with the silicon carbide semiconductor device, a gate leak current that flows when negative voltage with respect to the potential of the source electrode is applied to the gate electrode is limited to less than 2×10?11 A. The negative voltage applied to the gate electrode is limited to ?3V or lower relative to the potential of the source electrode.
    Type: Application
    Filed: January 23, 2019
    Publication date: September 19, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Keiji OKUMURA, Akimasa KINOSHITA
  • Publication number: 20190214457
    Abstract: A semiconductor device includes: a semiconductor substrate of a first conductivity type; a first semiconductor layer of the first conductivity type; a second semiconductor layer of a second conductivity type; a first semiconductor region of the first conductivity type; a trench; a second semiconductor region of the second conductivity type; a third semiconductor region of the second conductivity type; and a fourth semiconductor region of the first conductivity type. The second semiconductor region is selectively provided inside the first semiconductor layer, and the third semiconductor region is selectively provided inside the first semiconductor layer and contacts a bottom surface of the trench. The fourth semiconductor region is provided perpendicularly to a lengthwise direction of the trench in a plan view and is located at a depth position that is deeper than the second semiconductor region.
    Type: Application
    Filed: December 6, 2018
    Publication date: July 11, 2019
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Akimasa KINOSHITA, Keiji OKUMURA
  • Publication number: 20190189756
    Abstract: A silicon carbide semiconductor device includes an insulated-gate electrode structure that is formed inside a gate trench that goes through a base region and reaches a upper portion of a current transport layer to control a primary current flowing through the base region; a current suppression layer of the second conductivity type embedded within an upper portion of the current transport layer; a control electrode isolation insulating film filled into a control electrode isolation trench that goes through the base region and reaches an upper portion of the current suppression layer; and a control electrode pad disposed on the control electrode isolation insulating film, wherein an upper portion of the current suppression layer abuts a sidewall of the control electrode isolation insulating film, and a lower portion of the current suppression layer covers at least bottom corners of the control electrode isolation insulating film.
    Type: Application
    Filed: November 6, 2018
    Publication date: June 20, 2019
    Applicant: Fuji Electric Co., Ltd.
    Inventor: Keiji OKUMURA
  • Publication number: 20190181261
    Abstract: An insulated-gate semiconductor device includes: an n-type current spreading layer provided on an n?-type drift layer; a p+-type base region provided on the current spreading layer; an n+-type source region provided in an upper portion of the base region; an insulated-gate electrode structure provided inside a trench; a p+-type gate-bottom protection-region provided in the current spreading layer so as to be in contact with a bottom of the trench; and a p+-type base-bottom buried-region buried in the current spreading layer, having a bottom surface having the same depth as a bottom surface of the gate-bottom protection-region, wherein the base-bottom buried-region is divided into a plurality of portions in a depth direction through an n-type separation layer.
    Type: Application
    Filed: October 25, 2018
    Publication date: June 13, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji OKUMURA
  • Publication number: 20190181229
    Abstract: An insulated-gate semiconductor device, which has trenches arranged in a chip structure, the trenches defining both sidewalls in a first and second sidewall surface facing each other, includes: a first unit cell including a main-electrode region in contact with a first sidewall surface of a first trench, a base region in contact with a bottom surface of the main-electrode region and the first sidewall surface, a drift layer in contact with a bottom surface of the base region and the first sidewall surface, and a gate protection-region in contact with the second sidewall surface and a bottom surface of the first trench; and a second unit cell including an operation suppression region in contact with a first sidewall surface and a second sidewall surface of a second trench, wherein the second unit cell includes the second trench located at one end of an array of the trenches.
    Type: Application
    Filed: October 25, 2018
    Publication date: June 13, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji OKUMURA
  • Publication number: 20190172944
    Abstract: A semiconductor device includes a current spreading region of the first conductivity type provided on a drift layer and having a higher impurity density than the drift layer; a base region of a second conductivity type provided on the current spreading region; a base contact region of the second conductivity type provided in a top part of the base region and having a higher impurity density than the base region; and an electrode contact region of the first conductivity type provided in a top part of the base region that is laterally in contact with the base contact region, the electrode contact region having a higher impurity density than the drift layer, wherein a density of a second conductivity type impurity element in the base contact region is at least two times as much as a density of a first conductivity type impurity element in the electrode contact region.
    Type: Application
    Filed: November 6, 2018
    Publication date: June 6, 2019
    Applicant: Fuji Electric Co., Ltd.
    Inventor: Keiji OKUMURA
  • Publication number: 20190140093
    Abstract: This semiconductor device includes: an n-type SiC drift layer; a p-type base region; an n-type source region selectively embedded in the top part of the base region; p-type base contact regions selectively embedded in the top part of the base region so as to form a first gap with the source region along the <11-20> direction; a gate electrode provided via a gate insulating film; and an n-type drain region. The top surface of the drain region has an off-angle relative to the <11-20> direction towards the <0001> direction, and an alignment mark for positioning is formed on the top surface. The drift layer and the base region are epitaxially grown films, and a width wg of the first gap is set in accordance with a positional deviation width of the alignment mark caused by the off-angle and epitaxial growth.
    Type: Application
    Filed: October 24, 2018
    Publication date: May 9, 2019
    Applicant: Fuji Electric Co., Ltd.
    Inventor: Keiji OKUMURA
  • Publication number: 20190140091
    Abstract: An insulated-gate semiconductor device includes: an n+-type current spreading layer disposed on an n?-type drift layer; a p-type base region disposed on the current spreading layer; a n+-type main-electrode region arranged in an upper portion of the base region; an insulated-gate electrode structure provided in a trench; and a p+-type gate-bottom protection-region being in contact with a bottom of the trench, including a plurality of openings through which a part of the current spreading layer penetrates, being selectively buried in the current spreading layer, wherein positions of the openings cut on both sides of a central line of the trench are shifted from each other about the central line in a longitudinal direction of the trench in a planar pattern.
    Type: Application
    Filed: September 26, 2018
    Publication date: May 9, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Akimasa KINOSHITA, Yasuhiko OONISHI, Keiji OKUMURA
  • Publication number: 20190140095
    Abstract: A semiconductor device includes: an active area including a drift layer of a first conductivity type; and a voltage blocking area arranged around the active area and including an field relaxation region having a second conductivity type, being provided in an upper portion of the drift layer, wherein a depth of the field relaxation region decreases toward outside, and a spatial-modulation portion is provided at an outer end of the field relaxation region.
    Type: Application
    Filed: September 27, 2018
    Publication date: May 9, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji OKUMURA
  • Patent number: 10236372
    Abstract: A silicon carbide semiconductor device, including a silicon carbide substrate, multiple trenches provided in the silicon carbide substrate, a first semiconductor region provided between each adjacent two of the trenches, a second semiconductor region selectively provided in the first semiconductor region, multiple third semiconductor regions selectively provided in the silicon carbide substrate to each cover a bottom of one trench, multiple fourth semiconductor regions selectively provided in the silicon carbide substrate, each between adjacent two of the trenches and being in contact with the first semiconductor region, multiple gate electrodes, each provided via a gate insulating film in one of the trenches, a first electrode connected to the first and second semiconductor regions, and a second electrode connected to the rear surface of the silicon carbide substrate. At least two of the trenches are arranged between each adjacent two of the fourth semiconductor regions.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: March 19, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Keiji Okumura, Setsuko Wakimoto
  • Patent number: 10164021
    Abstract: A silicon carbide semiconductor device includes an n-type drift region made of SiC, n-type base regions, gate electrodes formed inside trenches with gate insulating films interposed therebetween, n-type source regions formed in upper portions of the base regions, an n-type drain region formed on the bottom of the drift region, p-type protection regions formed beneath the trenches, and p-type avalanche breakdown-inducing regions (first under-contact base regions) formed at the same depth as the protection regions and having the same impurity concentration as the protection regions. The width wcb of the avalanche breakdown-inducing regions and the width wtb of the protection regions satisfy the relationship wtb/wcb>4/3.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: December 25, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura
  • Publication number: 20180358454
    Abstract: A semiconductor device includes: an n-type drift region; a p-type base region above the drift region; a gate electrode disposed inside a trench above the drift region with a gate insulating film between the trench and the gate electrode; an n-type source region above the base region; a source electrode connected to the source region; an n-type drain region below the drift region; a drain electrode connected to the drain region; a p-type protective layer that is disposed inside the drift region and below the trench, the protective layer protruding beyond a trench width of the trench; and a p-type conductive path formation layer that is disposed between the protective layer and a bottom of the trench and protrudes beyond the trench width, the conductive path formation layer having protruding regions of which an impurity concentration therein is set so that an inversion layer is formed during ON.
    Type: Application
    Filed: May 8, 2018
    Publication date: December 13, 2018
    Applicant: Fuji Electric Co., Ltd.
    Inventor: Keiji OKUMURA
  • Publication number: 20180350781
    Abstract: A semiconductor device includes a MOSFET including a PN junction diode. A unipolar device is connected in parallel to the MOSFET and has two terminals. A first wire connects the PN junction diode to one of the two terminals of the unipolar device. A second wire connects the one of the two terminals of the unipolar device to an output line, so that the output line is connected to the MOSFET and the unipolar device via the first wire and the second wire. In one embodiment the connection of the first wire to the diode is with its anode, and in another the connection is with the cathode.
    Type: Application
    Filed: August 3, 2018
    Publication date: December 6, 2018
    Applicant: ROHM CO., LTD.
    Inventor: Keiji OKUMURA