Patents by Inventor Keiji Okumura

Keiji Okumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10672874
    Abstract: An insulated-gate semiconductor device, which has trenches arranged in a chip structure, the trenches defining both sidewalls in a first and second sidewall surface facing each other, includes: a first unit cell including a main-electrode region in contact with a first sidewall surface of a first trench, a base region in contact with a bottom surface of the main-electrode region and the first sidewall surface, a drift layer in contact with a bottom surface of the base region and the first sidewall surface, and a gate protection-region in contact with the second sidewall surface and a bottom surface of the first trench; and a second unit cell including an operation suppression region in contact with a first sidewall surface and a second sidewall surface of a second trench, wherein the second unit cell includes the second trench located at one end of an array of the trenches.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: June 2, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura
  • Publication number: 20200152748
    Abstract: In a trench-gate MOSFET, between a channel and an n+-type source region, an n-type shunt resistance region is provided in contact with the n+-type source region and the channel. The n+-type source region is disposed at a position separated from a gate insulating film at a side wall of a trench, in a direction parallel to a front surface of a semiconductor substrate. The n-type shunt resistance region is disposed, positioned deeper toward a drain electrode than is a front surface of the semiconductor substrate and shallower toward a source electrode than is the channel, and reaches a position deeper toward the drain electrode from the front surface of the semiconductor substrate than is the n+-type source region. The n-type shunt resistance region is a resistor for reducing current between the drain and the source when a large current exceeding a rated current flows during a short circuit.
    Type: Application
    Filed: September 23, 2019
    Publication date: May 14, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura
  • Publication number: 20200144227
    Abstract: A semiconductor device includes a MOSFET including a PN junction diode. A unipolar device is connected in parallel to the MOSFET and has two terminals. A first wire connects the PN junction diode to one of the two terminals of the unipolar device. A second wire connects the one of the two terminals of the unipolar device to an output line, so that the output line is connected to the MOSFET and the unipolar device via the first wire and the second wire. In one embodiment the connection of the first wire to the diode is with its anode, and in another the connection is with the cathode.
    Type: Application
    Filed: January 8, 2020
    Publication date: May 7, 2020
    Inventor: Keiji OKUMURA
  • Publication number: 20200119147
    Abstract: A trench gate MOSFET has at an n-type current spreading region between an n?-type drift region and a p-type base region, a first p+-type region facing a bottom of a trench, and a second p+-type region disposed between adjacent trenches. The first and the second p+-type regions extend parallel to a first direction in which the trench extends and are partially connected by a p+-type connecting portion and thus, disposed in a ladder shape when viewed from the front surface of a semiconductor substrate. The second p+-type region has at a portion of a surface on a drain side, a recessed portion that is recessed toward a source side. One or more recessed portions is provided between connection sites in the second p+-type region for connection with the p+-type connecting portions that are adjacent to each other in the first direction X.
    Type: Application
    Filed: August 23, 2019
    Publication date: April 16, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Akimasa KINOSHITA, Keiji Okumura
  • Patent number: 10600864
    Abstract: A semiconductor device includes: a semiconductor substrate of a first conductivity type; a first semiconductor layer of the first conductivity type; a second semiconductor layer of a second conductivity type; a first semiconductor region of the first conductivity type; a trench; a second semiconductor region of the second conductivity type; a third semiconductor region of the second conductivity type; and a fourth semiconductor region of the first conductivity type. The second semiconductor region is selectively provided inside the first semiconductor layer, and the third semiconductor region is selectively provided inside the first semiconductor layer and contacts a bottom surface of the trench. The fourth semiconductor region is provided perpendicularly to a lengthwise direction of the trench in a plan view and is located at a depth position that is deeper than the second semiconductor region.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: March 24, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Akimasa Kinoshita, Keiji Okumura
  • Publication number: 20200091339
    Abstract: In an inactive region of an active region, a gate pad, a gate poly-silicon layer, and a gate finger are provided at a front surface of a semiconductor substrate, via an insulating film. The gate poly-silicon layer is provided beneath the gate pad, sandwiching the insulating film therebetween. The gate pad, the gate poly-silicon layer, a gate finger, gate electrodes of a trench gate structure, a gate finger, and a second measurement pad are electrically connected in the order stated. As a result, the gate electrodes where parasitic resistance occurs and the gate poly-silicon layer where built-in resistance occurs are connected in series between the second measurement pad and the gate pad. A resistance value of the overall gate resistance that is a combined resistance of the built-in resistance and the parasitic resistance may be measured by the second measurement pad.
    Type: Application
    Filed: July 23, 2019
    Publication date: March 19, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji OKUMURA
  • Publication number: 20200091299
    Abstract: At an upper surface of a gate electrode, a recess occurs due to etching back of poly-silicon for forming the gate electrode. At an upper surface of an interlayer insulating film, a recess occurs in a portion that opposes in a depth direction, the recess of the upper surface of the gate electrode. A barrier metal includes sequentially stacked first to fourth metal films. The first metal film is a titanium nitride film that covers the surface of the interlayer insulating film and has an opening that exposes the recess of the upper surface of the interlayer insulating film. The second metal film is a titanium film that covers the first metal film and the source electrode, and is in contact with the interlayer insulating film, in the opening of the first metal film. The third and fourth metal films are a titanium nitride film and a titanium film, respectively.
    Type: Application
    Filed: July 24, 2019
    Publication date: March 19, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Shin'ichi NAKAMATA, Masanobu IWAYA, Keiji OKUMURA
  • Publication number: 20200058740
    Abstract: An insulated-gate semiconductor device, which has trenches arranged in a chip structure, the trenches defining both sidewalls in a first and second sidewall surface facing each other, includes: a first unit cell including a main-electrode region in contact with a first sidewall surface of a first trench, a base region in contact with a bottom surface of the main-electrode region and the first sidewall surface, a drift layer in contact with a bottom surface of the base region and the first sidewall surface, and a gate protection-region in contact with the second sidewall surface and a bottom surface of the first trench; and a second unit cell including an operation suppression region in contact with a first sidewall surface and a second sidewall surface of a second trench, wherein the second unit cell includes the second trench located at one end of an array of the trenches.
    Type: Application
    Filed: October 23, 2019
    Publication date: February 20, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura
  • Patent number: 10559552
    Abstract: A semiconductor device includes a MOSFET including a PN junction diode. A unipolar device is connected in parallel to the MOSFET and has two terminals. A first wire connects the PN junction diode to one of the two terminals of the unipolar device. A second wire connects the one of the two terminals of the unipolar device to an output line, so that the output line is connected to the MOSFET and the unipolar device via the first wire and the second wire. In one embodiment the connection of the first wire to the diode is with its anode, and in another the connection is with the cathode.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: February 11, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Keiji Okumura
  • Patent number: 10529848
    Abstract: An insulated-gate semiconductor device includes: an n-type current spreading layer provided on an n?-type drift layer; a p+-type base region provided on the current spreading layer; an n+-type source region provided in an upper portion of the base region; an insulated-gate electrode structure provided inside a trench; a p+-type gate-bottom protection-region provided in the current spreading layer so as to be in contact with a bottom of the trench; and a p+-type base-bottom buried-region buried in the current spreading layer, having a bottom surface having the same depth as a bottom surface of the gate-bottom protection-region, wherein the base-bottom buried-region is divided into a plurality of portions in a depth direction through an n-type separation layer.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: January 7, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura
  • Publication number: 20190371938
    Abstract: An insulated gate semiconductor device includes p+ gate bottom protection regions embedded in a drift layer at the bottoms of trenches that goes through n+ source regions and p-type base regions, and p+ base bottom embedded regions embedded in the drift layer below the base regions. The base bottom embedded regions have trapezoidal shapes due to a channeling phenomenon, and the bottom surfaces of the base bottom embedded regions are deeper than the bottom surfaces of the gate bottom protection regions.
    Type: Application
    Filed: August 20, 2019
    Publication date: December 5, 2019
    Applicant: Fuji Electric Co., Ltd.
    Inventor: Keiji OKUMURA
  • Patent number: 10490633
    Abstract: An insulated-gate semiconductor device, which has trenches arranged in a chip structure, the trenches defining both sidewalls in a first and second sidewall surface facing each other, includes: a first unit cell including a main-electrode region in contact with a first sidewall surface of a first trench, a base region in contact with a bottom surface of the main-electrode region and the first sidewall surface, a drift layer in contact with a bottom surface of the base region and the first sidewall surface, and a gate protection-region in contact with the second sidewall surface and a bottom surface of the first trench; and a second unit cell including an operation suppression region in contact with a first sidewall surface and a second sidewall surface of a second trench, wherein the second unit cell includes the second trench located at one end of an array of the trenches.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: November 26, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura
  • Patent number: 10483390
    Abstract: An insulated gate semiconductor device includes p+ gate bottom protection regions embedded in a drift layer at the bottoms of trenches that goes through n+ source regions and p-type base regions, and p+ base bottom embedded regions embedded in the drift layer below the base regions. The base bottom embedded regions have trapezoidal shapes due to a channeling phenomenon, and the bottom surfaces of the base bottom embedded regions are deeper than the bottom surfaces of the gate bottom protection regions.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: November 19, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura
  • Patent number: 10468509
    Abstract: A semiconductor device includes: an n-type drift region; a p-type base region above the drift region; a gate electrode disposed inside a trench above the drift region with a gate insulating film between the trench and the gate electrode; an n-type source region above the base region; a source electrode connected to the source region; an n-type drain region below the drift region; a drain electrode connected to the drain region; a p-type protective layer that is disposed inside the drift region and below the trench, the protective layer protruding beyond a trench width of the trench; and a p-type conductive path formation layer that is disposed between the protective layer and a bottom of the trench and protrudes beyond the trench width, the conductive path formation layer having protruding regions of which an impurity concentration therein is set so that an inversion layer is formed during ON.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: November 5, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura
  • Publication number: 20190288073
    Abstract: In a MOS silicon carbide semiconductor device and a silicon carbide semiconductor circuit device equipped with the silicon carbide semiconductor device, a gate leak current that flows when negative voltage with respect to the potential of the source electrode is applied to the gate electrode is limited to less than 2×10?11 A. The negative voltage applied to the gate electrode is limited to ?3V or lower relative to the potential of the source electrode.
    Type: Application
    Filed: January 23, 2019
    Publication date: September 19, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Keiji OKUMURA, Akimasa KINOSHITA
  • Publication number: 20190214457
    Abstract: A semiconductor device includes: a semiconductor substrate of a first conductivity type; a first semiconductor layer of the first conductivity type; a second semiconductor layer of a second conductivity type; a first semiconductor region of the first conductivity type; a trench; a second semiconductor region of the second conductivity type; a third semiconductor region of the second conductivity type; and a fourth semiconductor region of the first conductivity type. The second semiconductor region is selectively provided inside the first semiconductor layer, and the third semiconductor region is selectively provided inside the first semiconductor layer and contacts a bottom surface of the trench. The fourth semiconductor region is provided perpendicularly to a lengthwise direction of the trench in a plan view and is located at a depth position that is deeper than the second semiconductor region.
    Type: Application
    Filed: December 6, 2018
    Publication date: July 11, 2019
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Akimasa KINOSHITA, Keiji OKUMURA
  • Publication number: 20190189756
    Abstract: A silicon carbide semiconductor device includes an insulated-gate electrode structure that is formed inside a gate trench that goes through a base region and reaches a upper portion of a current transport layer to control a primary current flowing through the base region; a current suppression layer of the second conductivity type embedded within an upper portion of the current transport layer; a control electrode isolation insulating film filled into a control electrode isolation trench that goes through the base region and reaches an upper portion of the current suppression layer; and a control electrode pad disposed on the control electrode isolation insulating film, wherein an upper portion of the current suppression layer abuts a sidewall of the control electrode isolation insulating film, and a lower portion of the current suppression layer covers at least bottom corners of the control electrode isolation insulating film.
    Type: Application
    Filed: November 6, 2018
    Publication date: June 20, 2019
    Applicant: Fuji Electric Co., Ltd.
    Inventor: Keiji OKUMURA
  • Publication number: 20190181261
    Abstract: An insulated-gate semiconductor device includes: an n-type current spreading layer provided on an n?-type drift layer; a p+-type base region provided on the current spreading layer; an n+-type source region provided in an upper portion of the base region; an insulated-gate electrode structure provided inside a trench; a p+-type gate-bottom protection-region provided in the current spreading layer so as to be in contact with a bottom of the trench; and a p+-type base-bottom buried-region buried in the current spreading layer, having a bottom surface having the same depth as a bottom surface of the gate-bottom protection-region, wherein the base-bottom buried-region is divided into a plurality of portions in a depth direction through an n-type separation layer.
    Type: Application
    Filed: October 25, 2018
    Publication date: June 13, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji OKUMURA
  • Publication number: 20190181229
    Abstract: An insulated-gate semiconductor device, which has trenches arranged in a chip structure, the trenches defining both sidewalls in a first and second sidewall surface facing each other, includes: a first unit cell including a main-electrode region in contact with a first sidewall surface of a first trench, a base region in contact with a bottom surface of the main-electrode region and the first sidewall surface, a drift layer in contact with a bottom surface of the base region and the first sidewall surface, and a gate protection-region in contact with the second sidewall surface and a bottom surface of the first trench; and a second unit cell including an operation suppression region in contact with a first sidewall surface and a second sidewall surface of a second trench, wherein the second unit cell includes the second trench located at one end of an array of the trenches.
    Type: Application
    Filed: October 25, 2018
    Publication date: June 13, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji OKUMURA
  • Publication number: 20190172944
    Abstract: A semiconductor device includes a current spreading region of the first conductivity type provided on a drift layer and having a higher impurity density than the drift layer; a base region of a second conductivity type provided on the current spreading region; a base contact region of the second conductivity type provided in a top part of the base region and having a higher impurity density than the base region; and an electrode contact region of the first conductivity type provided in a top part of the base region that is laterally in contact with the base contact region, the electrode contact region having a higher impurity density than the drift layer, wherein a density of a second conductivity type impurity element in the base contact region is at least two times as much as a density of a first conductivity type impurity element in the electrode contact region.
    Type: Application
    Filed: November 6, 2018
    Publication date: June 6, 2019
    Applicant: Fuji Electric Co., Ltd.
    Inventor: Keiji OKUMURA