Patents by Inventor Keiji Okumura

Keiji Okumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180358454
    Abstract: A semiconductor device includes: an n-type drift region; a p-type base region above the drift region; a gate electrode disposed inside a trench above the drift region with a gate insulating film between the trench and the gate electrode; an n-type source region above the base region; a source electrode connected to the source region; an n-type drain region below the drift region; a drain electrode connected to the drain region; a p-type protective layer that is disposed inside the drift region and below the trench, the protective layer protruding beyond a trench width of the trench; and a p-type conductive path formation layer that is disposed between the protective layer and a bottom of the trench and protrudes beyond the trench width, the conductive path formation layer having protruding regions of which an impurity concentration therein is set so that an inversion layer is formed during ON.
    Type: Application
    Filed: May 8, 2018
    Publication date: December 13, 2018
    Applicant: Fuji Electric Co., Ltd.
    Inventor: Keiji OKUMURA
  • Publication number: 20180350781
    Abstract: A semiconductor device includes a MOSFET including a PN junction diode. A unipolar device is connected in parallel to the MOSFET and has two terminals. A first wire connects the PN junction diode to one of the two terminals of the unipolar device. A second wire connects the one of the two terminals of the unipolar device to an output line, so that the output line is connected to the MOSFET and the unipolar device via the first wire and the second wire. In one embodiment the connection of the first wire to the diode is with its anode, and in another the connection is with the cathode.
    Type: Application
    Filed: August 3, 2018
    Publication date: December 6, 2018
    Applicant: ROHM CO., LTD.
    Inventor: Keiji OKUMURA
  • Publication number: 20180350976
    Abstract: An insulated gate semiconductor device includes p+ gate bottom protection regions embedded in a drift layer at the bottoms of trenches that goes through n+ source regions and p-type base regions, and p+ base bottom embedded regions embedded in the drift layer below the base regions. The base bottom embedded regions have trapezoidal shapes due to a channeling phenomenon, and the bottom surfaces of the base bottom embedded regions are deeper than the bottom surfaces of the gate bottom protection regions.
    Type: Application
    Filed: May 8, 2018
    Publication date: December 6, 2018
    Applicant: Fuji Electric Co., Ltd.
    Inventor: Keiji OKUMURA
  • Publication number: 20180342587
    Abstract: A silicon carbide semiconductor device includes an n-type drift region made of SiC, n-type base regions, gate electrodes formed inside trenches with gate insulating films interposed therebetween, n-type source regions formed in upper portions of the base regions, an n-type drain region formed on the bottom of the drift region, p-type protection regions formed beneath the trenches, and p-type avalanche breakdown-inducing regions (first under-contact base regions) formed at the same depth as the protection regions and having the same impurity concentration as the protection regions. The width wcb of the avalanche breakdown-inducing regions and the width wtb of the protection regions satisfy the relationship wtb/wcb>4/3.
    Type: Application
    Filed: April 6, 2018
    Publication date: November 29, 2018
    Applicant: Fuji Electric Co., Ltd.
    Inventor: Keiji OKUMURA
  • Patent number: 10074634
    Abstract: A semiconductor device includes a MOSFET including a PN junction diode. A unipolar device is connected in parallel to the MOSFET and has two terminals. A first wire connects the PN junction diode to one of the two terminals of the unipolar device. A second wire connects the one of the two terminals of the unipolar device to an output line, so that the output line is connected to the MOSFET and the unipolar device via the first wire and the second wire. In one embodiment the connection of the first wire to the diode is with its anode, and in another the connection is with the cathode.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: September 11, 2018
    Assignee: ROHM CO., LTD.
    Inventor: Keiji Okumura
  • Publication number: 20180190624
    Abstract: A semiconductor device includes a MOSFET including a PN junction diode. A unipolar device is connected in parallel to the MOSFET and has two terminals. A first wire connects the PN junction diode to one of the two terminals of the unipolar device. A second wire connects the one of the two terminals of the unipolar device to an output line, so that the output line is connected to the MOSFET and the unipolar device via the first wire and the second wire. In one embodiment the connection of the first wire to the diode is with its anode, and in another the connection is with the cathode.
    Type: Application
    Filed: February 28, 2018
    Publication date: July 5, 2018
    Applicant: ROHM CO., LTD.
    Inventor: Keiji OKUMURA
  • Patent number: 10009491
    Abstract: The operation unit (5) is configured to receive user's operation and supported at a position frontward of the image reading unit (2) by the support housing (10) so as to be rotatable within a predetermined rotation range around a rotation shaft parallel to a right-left direction of the image formation apparatus (100). The information reading unit (6) is configured to read information about the user and housed in the housing side surface (12) so that a part of the information reading unit (6) is present rearward of the operation unit (5) in a first attitude in which a surface of the operation unit (5) is closest to a vertical plane, and a part of the information reading unit (6) is present downward of the operation unit (5) in a second attitude in which the surface of the operation unit (5) is closest to a horizontal plane.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: June 26, 2018
    Assignee: KYOCERA Document Solutions Inc.
    Inventors: Hirofumi Kuroki, Mikiya Kitagawa, Keiji Okumura
  • Patent number: 10002952
    Abstract: A silicon carbide (SiC) semiconductor device, including a SiC substrate, a first SiC layer formed on the substrate, first and second impurity layers selectively formed in the first SiC layer, a second SiC layer formed on the first SiC layer, a third impurity layer selectively formed in the second SiC layer and on the second impurity layer, a third SiC layer formed on the second SiC layer, a fourth impurity layer selectively formed in the third SiC layer, a trench that penetrates the fourth impurity layer and the second and third SiC layers, a bottom thereof reaching the first impurity layer, and a gate electrode formed in the trench via a gate insulating film. The first SiC layer has first and second regions adjacent respectively to the first and second impurity layers on a side facing the substrate, an impurity concentration at the first region being lower than that at the second region.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: June 19, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yoshiyuki Sugahara, Keiji Okumura
  • Patent number: 9917074
    Abstract: A semiconductor device includes a MOSFET including a PN junction diode. A unipolar device is connected in parallel to the MOSFET and has two terminals. A first wire connects the PN junction diode to one of the two terminals of the unipolar device. A second wire connects the one of the two terminals of the unipolar device to an output line, so that the output line is connected to the MOSFET and the unipolar device via the first wire and the second wire. In one embodiment the connection of the first wire to the diode is with its anode, and in another the connection is with the cathode.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: March 13, 2018
    Assignee: ROHM CO., LTD.
    Inventor: Keiji Okumura
  • Patent number: 9916076
    Abstract: A display control unit (23) scrollably displays a plurality of images to be displayed in a specific display area within a screen. An operation receiving unit (21) receives a scroll instruction and a display mode switching instruction that are issued in response to a user operation. When a display mode is switched, the display control unit (23) switches a display in the display area such that, among the plurality of images in the display area displayed in the first display mode, at least one image located as a position that goes out of the display area first upon scroll in a forward direction is arranged, upon a switch to a second display mode, at a position that also goes out of the display area first upon scroll in the forward direction in the display area.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: March 13, 2018
    Assignee: OLYMPUS CORPORATION
    Inventors: Keiji Okumura, Koichi Hirose, Toshiya Nishimura
  • Publication number: 20180033885
    Abstract: A silicon carbide semiconductor device, including a silicon carbide substrate, multiple trenches provided in the silicon carbide substrate, a first semiconductor region provided between each adjacent two of the trenches, a second semiconductor region selectively provided in the first semiconductor region, multiple third semiconductor regions selectively provided in the silicon carbide substrate to each cover a bottom of one trench, multiple fourth semiconductor regions selectively provided in the silicon carbide substrate, each between adjacent two of the trenches and being in contact with the first semiconductor region, multiple gate electrodes, each provided via a gate insulating film in one of the trenches, a first electrode connected to the first and second semiconductor regions, and a second electrode connected to the rear surface of the silicon carbide substrate. At least two of the trenches are arranged between each adjacent two of the fourth semiconductor regions.
    Type: Application
    Filed: June 22, 2017
    Publication date: February 1, 2018
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Keiji OKUMURA, Setsuko WAKIMOTO
  • Publication number: 20180033876
    Abstract: A silicon carbide (SiC) semiconductor device, including a SiC substrate, a first SiC layer formed on the substrate, first and second impurity layers selectively formed in the first SiC layer, a second SiC layer formed on the first SiC layer, a third impurity layer selectively formed in the second SiC layer and on the second impurity layer, a third SiC layer formed on the second SiC layer, a fourth impurity layer selectively formed in the third SiC layer, a trench that penetrates the fourth impurity layer and the second and third SiC layers, a bottom thereof reaching the first impurity layer, and a gate electrode formed in the trench via a gate insulating film. The first SiC layer has first and second regions adjacent respectively to the first and second impurity layers on a side facing the substrate, an impurity concentration at the first region being lower than that at the second region.
    Type: Application
    Filed: May 31, 2017
    Publication date: February 1, 2018
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yoshiyuki SUGAHARA, Keiji OKUMURA
  • Publication number: 20180013905
    Abstract: The operation unit (5) is configured to receive user's operation and supported at a position frontward of the image reading unit (2) by the support housing (10) so as to be rotatable within a predetermined rotation range around a rotation shaft parallel to a right-left direction of the image formation apparatus (100). The information reading unit (6) is configured to read information about the user and housed in the housing side surface (12) so that a part of the information reading unit (6) is present rearward of the operation unit (5) in a first attitude in which a surface of the operation unit (5) is closest to a vertical plane, and a part of the information reading unit (6) is present downward of the operation unit (5) in a second attitude in which the surface of the operation unit (5) is closest to a horizontal plane.
    Type: Application
    Filed: April 1, 2016
    Publication date: January 11, 2018
    Inventors: Hirofumi Kuroki, Mikiya Kitagawa, Keiji Okumura
  • Publication number: 20170263590
    Abstract: A semiconductor device includes a MOSFET including a PN junction diode. A unipolar device is connected in parallel to the MOSFET and has two terminals. A first wire connects the PN junction diode to one of the two terminals of the unipolar device. A second wire connects the one of the two terminals of the unipolar device to an output line, so that the output line is connected to the MOSFET and the unipolar device via the first wire and the second wire. In one embodiment the connection of the first wire to the diode is with its anode, and in another the connection is with the cathode.
    Type: Application
    Filed: May 31, 2017
    Publication date: September 14, 2017
    Applicant: ROHM CO., LTD.
    Inventor: Keiji OKUMURA
  • Patent number: 9679877
    Abstract: A semiconductor device includes a MOSFET including a PN junction diode. A unipolar device is connected in parallel to the MOSFET and has two terminals. A first wire connects the PN junction diode to one of the two terminals of the unipolar device. A second wire connects the one of the two terminals of the unipolar device to an output line, so that the output line is connected to the MOSFET and the unipolar device via the first wire and the second wire. In one embodiment the connection of the first wire to the diode is with its anode, and in another the connection is with the cathode.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: June 13, 2017
    Assignee: ROHM CO., LTD.
    Inventor: Keiji Okumura
  • Publication number: 20170092743
    Abstract: A method for producing a semiconductor power device, includes forming a gate trench from a surface of a semiconductor layer toward an inside thereof. A first insulation film is formed on an inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.
    Type: Application
    Filed: September 9, 2016
    Publication date: March 30, 2017
    Applicant: ROHM CO., LTD.
    Inventors: Keiji OKUMURA, Mineo MIURA, Yuki NAKANO, Noriaki KAWAMOTO, Hidetoshi ABE
  • Publication number: 20170018536
    Abstract: A semiconductor device includes a MOSFET including a PN junction diode. A unipolar device is connected in parallel to the MOSFET and has two terminals. A first wire connects the PN junction diode to one of the two terminals of the unipolar device. A second wire connects the one of the two terminals of the unipolar device to an output line, so that the output line is connected to the MOSFET and the unipolar device via the first wire and the second wire. In one embodiment the connection of the first wire to the diode is with its anode, and in another the connection is with the cathode.
    Type: Application
    Filed: September 28, 2016
    Publication date: January 19, 2017
    Applicant: ROHM CO., LTD.
    Inventor: Keiji OKUMURA
  • Patent number: 9494910
    Abstract: An image forming apparatus includes an apparatus main body and a board holding member. The apparatus main body includes an image forming part. The board holding member is attached to the apparatus main body and configured to have a surface to which a board is fixed. The apparatus main body includes an engaging part and a supporting part. The engaging part is configured to engage with a side edge part of the board holding member. The supporting part is configured to support a part closer to an inside than the side edge part of the board holding member. The board holding member is rotated around the side edge part as a fulcrum so as to be opened and closed with respect to the apparatus main body.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: November 15, 2016
    Assignee: KYOCERA Document Solutions Inc.
    Inventors: Shinobu Ohata, Keiji Okumura
  • Patent number: 9461021
    Abstract: A semiconductor device includes a first chip including a PN junction diode, and a second chip including a Schottky barrier diode, connected in parallel to the first chip. A first inductive metal member has a first end connected to a cathode of the PN junction diode, and a second end connected to a cathode of the Schottky barrier diode. A second inductive metal member has a third end connected to the cathode of the Schottky barrier diode. An output line is connected to a fourth end of the second connection member, and electrically connected to the cathode of the PN junction diode via a first path formed by the first and second metal members, and to the cathode of the Schottky barrier diode via a second path formed by the second metal member and exclusive of the first metal member, so that the first path has greater inductance than the second.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: October 4, 2016
    Assignee: ROHM CO., LTD.
    Inventor: Keiji Okumura
  • Patent number: 9454129
    Abstract: An image forming apparatus includes an exterior cover having a plurality of faces. The exterior cover is configured so that one face of the plurality of faces is divided into a plurality of cover boards. The plurality of cover boards are configured so that adjacent cover boards of the plurality of cover boards include respective overlapping parts overlapping onto each other formed in the respective adjacent cover boards and the one face is composed by overlapping the overlapping parts from the outside in predetermined order.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: September 27, 2016
    Assignee: KYOCERA Document Solutions Inc.
    Inventor: Keiji Okumura