Patents by Inventor Keisuke Nakazawa

Keisuke Nakazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8080463
    Abstract: A semiconductor device manufacturing method has forming element isolation trenches in a semiconductor substrate, forming a silicon compound film in insides of the element isolation trenches in order to embed the element isolation trenches, conducting a first oxidation processing at a first temperature to reform a surface of the silicon compound film to a volatile matter emission preventing layer which permits passage of an oxidizing agent and impurities and which does not permit passage of a volatile matter containing silicon atoms, and conducting a second oxidation processing at a second temperature which is higher than the first temperature to form a coated silicon oxide film inside the element isolation trenches.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: December 20, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuaki Iwasawa, Takeshi Hoshi, Keisuke Nakazawa, Shogo Matsuo, Takashi Nakao, Ryu Kato, Tetsuya Kai, Katsuyuki Sekine
  • Publication number: 20100311220
    Abstract: A method for manufacturing semiconductor device has forming a plurality of trenches having at least two kinds of aspect ratios on a semiconductor substrate, filling the plurality of trenches with a coating material containing silicon, forming a mask on the coating material in a part of the trenches among the plurality of trenches filled with the coating material, implanting an ion for accelerating oxidation of the coating material into the coating material in the trenches on which the mask is not formed, forming a first insulating film by oxidizing the coating materials into which the ion is implanted, removing the coating material from the part of the trenches after removing the mask and forming a second insulating film in the part of the trenches from which the coating material is removed.
    Type: Application
    Filed: March 23, 2010
    Publication date: December 9, 2010
    Inventors: Shogo MATSUO, Takeshi Hoshi, Keisuke Nakazawa, Kazuaki Iwasawa
  • Patent number: 7781341
    Abstract: A method for manufacturing a semiconductor device is provided, which includes feeding a coating liquid comprising a silicon-containing compound dissolved in a solvent onto a semiconductor substrate, revolving the semiconductor substrate to form a coated film containing the silicon-containing compound, feeding a rinsing liquid at least partially comprising ?-pinene onto the underside of the semiconductor substrate to perform back-rinsing and washing of the underside of the semiconductor substrate, drying the semiconductor substrate that has been back-rinsed to remove the rinsing liquid, and heat-treating the semiconductor substrate to remove the solvent from the coated film to obtain an insulating film containing the silicon-containing compound.
    Type: Grant
    Filed: September 26, 2006
    Date of Patent: August 24, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Keisuke Nakazawa
  • Publication number: 20100190317
    Abstract: A semiconductor device manufacturing method has forming element isolation trenches in a semiconductor substrate, forming a silicon compound film in insides of the element isolation trenches in order to embed the element isolation trenches, conducting a first oxidation processing at a first temperature to reform a surface of the silicon compound film to a volatile matter emission preventing layer which permits passage of an oxidizing agent and impurities and which does not permit passage of a volatile matter containing silicon atoms, and conducting a second oxidation processing at a second temperature which is higher than the first temperature to form a coated silicon oxide film inside the element isolation trenches.
    Type: Application
    Filed: January 21, 2010
    Publication date: July 29, 2010
    Inventors: Kazuaki IWASAWA, Takeshi Hoshi, Keisuke Nakazawa, Shogo Matsuo, Takashi Nakao, Ryu Kato, Tetsuya Kai, Katsuyuki Sekine
  • Publication number: 20090226615
    Abstract: A spin coating apparatus that supplies a coating liquid to a substrate and rotating the substrate to form a coating film, has a holding part that holds the substrate mounted thereon in a horizontal position; a rotationally driving source that rotationally drives the holding part about a rotational axis parallel with the vertical direction, thereby rotating the substrate; and a coating liquid supplying part that supplies the coating liquid to the substrate held by the holding part.
    Type: Application
    Filed: March 3, 2009
    Publication date: September 10, 2009
    Inventor: Keisuke Nakazawa
  • Patent number: 7531408
    Abstract: A method of manufacturing a semiconductor device, including forming a capacitor above a semiconductor substrate, the capacitor including a dielectric film containing Pb, Zr, Ti and O. Forming the capacitor includes forming a crystallized film which contains Pb, Sr, Zr, Ti, Ru and O.
    Type: Grant
    Filed: May 25, 2007
    Date of Patent: May 12, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keisuke Nakazawa, Koji Yamakawa, Katsuaki Natori, Soichi Yamazaki, Hiroshi Itokawa, Hiroyuki Kanaya
  • Publication number: 20090036629
    Abstract: Disclosed is a method of manufacturing a semiconductor device comprising forming an element isolation trench in a semiconductor substrate, coating a polysilazane perhydride solution on the semiconductor substrate having the element isolation trench formed thereon to form a polysilazane perhydride film, the polysilazane perhydride solution comprising dibutyl ether having a butanol concentration of 30 ppm or less, and polysilazane perhydride dissolved in the dibutyl ether, subjecting the polysilazane perhydride film to oxidation in an atmosphere containing water vapor to form a silicon dioxide film, and selectively removing the silicon dioxide film to leave the silicon dioxide film in the element isolation trench to form an element isolating insulation film.
    Type: Application
    Filed: June 25, 2008
    Publication date: February 5, 2009
    Inventors: Atsuko Kawasaki, Masahiro Kiyotoshi, Keisuke Nakazawa, Osamu Arisumi, Jakeshi Hoshi, Katsuhiko Tachibana
  • Patent number: 7407864
    Abstract: Disclosed is a method of manufacturing a semiconductor device comprising forming an element isolation trench in a semiconductor substrate, coating a polysilazane perhydride solution on the semiconductor substrate having the element isolation trench formed thereon to form a polysilazane perhydride film, the polysilazane perhydride solution comprising dibutyl ether having a butanol concentration of 30 ppm or less, and polysilazane perhydride dissolved in the dibutyl ether, subjecting the polysilazane perhydride film to oxidation in an atmosphere containing water vapor to form a silicon dioxide film, and selectively removing the silicon dioxide film to leave the silicon dioxide film in the element isolation trench to form an element isolating insulation film.
    Type: Grant
    Filed: July 7, 2005
    Date of Patent: August 5, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Kawasaki, Masahiro Kiyotoshi, Keisuke Nakazawa, Osamu Arisumi, Takeshi Hoshi, Katsuhiko Tachibana
  • Patent number: 7378329
    Abstract: Disclosed is a method for manufacturing a semiconductor device, comprising forming an insulating film above a semiconductor substrate having an element formed thereon, forming an anti-reflection layer that is impermeable to hydrogen on the insulating film, the anti-reflection layer comprising a layer formed of at least one material selected from the group consisting of silicon nitride, silicon oxynitride, chromium oxide, CrOxFy, CrAlxOy, AlSixOy, ZrSixOy, silicon oxycarbide, carbon, chromium nitride, titanium nitride, tantalum nitride, aluminum nitride, TiAlxNy, TaAlxNy, TiSixNy, AlSixNy (where x and y denote the component ratio), and silicon carbide, forming a resist pattern on the anti-reflection layer, forming a hole in the insulating film with the resist pattern used as a mask, burying a conductive material in the hole to form a plug, removing the resist pattern, and forming a ferroelectric capacitor above the anti-reflection layer.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: May 27, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keisuke Nakazawa, Soichi Yamazaki
  • Publication number: 20080090988
    Abstract: A method for handling polysilazane or a polysilazane solution includes synthesizing polysilazane and preparing the polysilazane solution in a first space isolated from outside air. The first space is mainly supplied with air from which amine, basic substance, volatile organic compound and acidic substance are eliminated.
    Type: Application
    Filed: September 27, 2007
    Publication date: April 17, 2008
    Inventors: Keisuke Nakazawa, Katsuhiko Tachibana, Takeshi Hoshi, Masahiro Kiyotoshi, Atsuko Kawasaki, Osamu Arisumi
  • Publication number: 20070231948
    Abstract: A method of manufacturing a semiconductor device, including forming a capacitor above a semiconductor substrate, the capacitor including a dielectric film containing Pb, Zr, Ti and O. Forming the capacitor includes forming a crystallized film which contains Pb, Sr, Zr, Ti, Ru and O.
    Type: Application
    Filed: May 25, 2007
    Publication date: October 4, 2007
    Applicant: KABUSHHIKI KAISHA TOSHIBA
    Inventors: Keisuke Nakazawa, Koji Yamakawa, Katsuaki Natori, Soichi Yamazaki, Hiroshi Itokawa, Hiroyuki Kanaya
  • Publication number: 20070212894
    Abstract: A method for manufacturing a semiconductor device is provided, which includes feeding a coating liquid comprising a silicon-containing compound dissolved in a solvent onto a semiconductor substrate, revolving the semiconductor substrate to form a coated film containing the silicon-containing compound, feeding a rinsing liquid at least partially comprising ?-pinene onto the underside of the semiconductor substrate to perform back-rinsing and washing of the underside of the semiconductor substrate, drying the semiconductor substrate that has been back-rinsed to remove the rinsing liquid, and heat-treating the semiconductor substrate to remove the solvent from the coated film to obtain an insulating film containing the silicon-containing compound.
    Type: Application
    Filed: September 26, 2006
    Publication date: September 13, 2007
    Inventor: Keisuke Nakazawa
  • Patent number: 7259094
    Abstract: An apparatus for manufacturing a semiconductor device is disclosed which comprises a chamber which holds a to-be-processed substrate having a film containing at least one kind of metal element which will become a component of a volatile metal compound, a heater which heats the substrate held in the chamber, and an adsorbent which is provided in the chamber and which adsorbs the volatile metal compound generated from the film by heating the substrate.
    Type: Grant
    Filed: April 21, 2005
    Date of Patent: August 21, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuaki Natori, Keisuke Nakazawa, Koji Yamakawa, Hiroyuki Kanaya, Yoshinori Kumura, Hiroshi Itokawa, Osamu Arisumi
  • Patent number: 7233040
    Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, and a capacitor provided above the semiconductor substrate and including a film which contains Pb, Sr, Zr, Ti, Ru and O and a dielectric film which contains Pb, Zr, Ti and O and which is provided on the film containing Pb, Sr, Zr, Ti, Ru and O.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: June 19, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keisuke Nakazawa, Koji Yamakawa, Katsuaki Natori, Soichi Yamazaki, Hiroshi Itokawa, Hiroyuki Kanaya
  • Patent number: 7183601
    Abstract: Disclosed in a semiconductor device comprising a semiconductor substrate, and a ferroelectric layer provided above the semiconductor substrate and sandwiched between a lower electrode and an upper electrode, the lower electrode comprising a strontium ruthenate film having a thickness of 2 nm or less.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: February 27, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Keisuke Nakazawa
  • Publication number: 20060205165
    Abstract: Disclosed is a method of manufacturing a semiconductor device comprising forming an element isolation trench in a semiconductor substrate, coating a polysilazane perhydride solution on the semiconductor substrate having the element isolation trench formed thereon to form a polysilazane perhydride film, the polysilazane perhydride solution comprising dibutyl ether having a butanol concentration of 30 ppm or less, and polysilazane perhydride dissolved in the dibutyl ether, subjecting the polysilazane perhydride film to oxidation in an atmosphere containing water vapor to form a silicon dioxide film, and selectively removing the silicon dioxide film to leave the silicon dioxide film in the element isolation trench to form an element isolating insulation film.
    Type: Application
    Filed: July 7, 2005
    Publication date: September 14, 2006
    Inventors: Atsuko Kawasaki, Masahiro Kiyotoshi, Keisuke Nakazawa, Osamu Arisumi, Takeshi Hoshi, Katsuhiko Tachibana
  • Patent number: 7105400
    Abstract: There is disclosed a method of manufacturing a semiconductor device, comprising forming an underlying region including an interlevel insulating film on a semiconductor substrate, forming an alumina film on the underlying region, forming a hole in the alumina film, filling the hole with a bottom electrode film, forming a dielectric film on the bottom electrode film, and forming a top electrode film on the dielectric film.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: September 12, 2006
    Assignees: Kabushiki Kaisha Toshiba, Infineon Technologies, AG
    Inventors: Keitaro Imai, Koji Yamakawa, Hiroshi Itokawa, Katsuaki Natori, Osamu Arisumi, Keisuke Nakazawa, Bum-ki Moon
  • Publication number: 20050277208
    Abstract: Disclosed is a method for manufacturing a semiconductor device, comprising forming an insulating film above a semiconductor substrate having an element formed thereon, forming an anti-reflection layer that is impermeable to hydrogen on the insulating film, the anti-reflection layer comprising a layer formed of at least one material selected from the group consisting of silicon nitride, silicon oxynitride, chromium oxide, CrOxFy, CrAlxOy, AlSixOy, ZrSixOy, silicon oxycarbide, carbon, chromium nitride, titanium nitride, tantalum nitride, aluminum nitride, TiAlxNy, TaAlxNy, TiSixNy, AlSixNy (where x and y denote the component ratio), and silicon carbide, forming a resist pattern on the anti-reflection layer, forming a hole in the insulating film with the resist pattern used as a mask, burying a conductive material in the hole to form a plug, removing the resist pattern, and forming a ferroelectric capacitor above the anti-reflection layer.
    Type: Application
    Filed: September 3, 2004
    Publication date: December 15, 2005
    Inventors: Keisuke Nakazawa, Soichi Yamazaki
  • Publication number: 20050224851
    Abstract: Disclosed in a semiconductor device comprising a semiconductor substrate, and a ferroelectric layer provided above the semiconductor substrate and sandwiched between a lower electrode and an upper electrode, the lower electrode comprising a strontium ruthenate film having a thickness of 2 nm or less.
    Type: Application
    Filed: June 14, 2004
    Publication date: October 13, 2005
    Inventor: Keisuke Nakazawa
  • Publication number: 20050186767
    Abstract: An apparatus for manufacturing a semiconductor device is disclosed which comprises a chamber which holds a to-be-processed substrate having a film containing at least one kind of metal element which will become a component of a volatile metal compound, a heater which heats the substrate held in the chamber, and an adsorbent which is provided in the chamber and which adsorbs the volatile metal compound generated from the film by heating the substrate.
    Type: Application
    Filed: April 21, 2005
    Publication date: August 25, 2005
    Inventors: Katsuaki Natori, Keisuke Nakazawa, Koji Yamakawa, Hiroyuki Kanaya, Yoshinori Kumura, Hiroshi Itokawa, Osamu Arisumi