Abstract: Laterally-gated transistors and lateral Schottky diodes are disclosed. The FET includes a substrate, source and drain electrodes, channel, a gate electrode structure, and a dielectric layer. The gate electrode structure includes an electrode in contact with the channel and a lateral field plate adjacent to the electrode. The dielectric layer is disposed between the lateral field plate and the channel. The lateral field plate contacts the dielectric layer and to modulate an electric field proximal to the gate electrode proximal to the drain or source electrodes. Also disclosed is a gate electrode structure with lateral field plates symmetrically disposed relative to the gate electrode. Also disclosed in a substrate with dielectric structures buried in the substrate remote from the gate electrode structure. A lateral Schottky diode having an anode structure includes an anode (A), cathodes (C) and lateral field plates located between the anode and the cathodes.

Abstract: A FET with buried gate structures which contact an epitaxial channel layer only from the sides. The epitaxial channel layer preferably comprises multiple channel segments, the widths of which vary along the depth direction. By controlling the slope of the channel sidewalls and the distance between buried gate structures, the FET's transfer characteristics can be engineered to improve the FET's linearity.

Abstract: An ohmic contact for a multiple channel FET comprises a plurality of slit-shaped recesses in a wafer on which a multiple channel FET resides, with each recess having a depth at least equal to the depth of the lowermost channel layer. Ohmic metals in and on the sidewalls of each recess provide ohmic contact to each of the multiple channel layers. An ohmic metal-filled linear connecting recess contiguous with the outside edge of each recess may be provided, as well as an ohmic metal contact layer on the top surface of the wafer over and in contact with the ohmic metals in each of the recesses. The present ohmic contact typically serves as a source and/or drain contact for the multiple channel FET. Also described is the use of a regrown material to make ohmic contact with multiple channels, with the regrown material preferably having a corrugated structure.

Abstract: An iron rivet including a head and a shank, an aluminum plate, an iron plate, and first and second electrodes are prepared. A sandwiching step of sandwiching the rivet, the aluminum plate, and the iron plate between the first electrode and the second electrode, a penetration step of performing pressurization and current application by the first and second electrodes so that the shank penetrates through the aluminum plate, and a forming step of performing pressurization and current application by the first and second electrodes so that a nugget is formed between the shank and the iron plate are included. In the penetration step, the pressurization and current application is performed while air is blown to a side face of the shank so that the air hits a region around a boundary between the shank and the aluminum plate.

Abstract: Laterally-gated transistors and lateral Schottky diodes are disclosed. The FET includes a substrate, source and drain electrodes, channel, a gate electrode structure, and a dielectric layer. The gate electrode structure includes an electrode in contact with the channel and a lateral field plate adjacent to the electrode. The dielectric layer is disposed between the lateral field plate and the channel. The lateral field plate contacts the dielectric layer and to modulate an electric field proximal to the gate electrode proximal to the drain or source electrodes. Also disclosed is a gate electrode structure with lateral field plates symmetrically disposed relative to the gate electrode. Also disclosed in a substrate with dielectric structures buried in the substrate remote from the gate electrode structure. A lateral Schottky diode having an anode structure includes an anode (A), cathodes (C) and lateral field plates located between the anode and the cathodes.

Abstract: An ohmic contact for a multiple channel FET comprises a plurality of slit-shaped recesses in a wafer on which a multiple channel FET resides, with each recess having a depth at least equal to the depth of the lowermost channel layer. Ohmic metals in and on the sidewalls of each recess provide ohmic contact to each of the multiple channel layers. An ohmic metal-filled linear connecting recess contiguous with the outside edge of each recess may be provided, as well as an ohmic metal contact layer on the top surface of the wafer over and in contact with the ohmic metals in each of the recesses. The present ohmic contact typically serves as a source and/or drain contact for the multiple channel FET. Also described is the use of a regrown material to make ohmic contact with multiple channels, with the regrown material preferably having a corrugated structure.

Abstract: A silver-plated product is produced by forming a surface layer of silver on a base material by electroplating at a liquid temperature of 10 to 35° C. and a current density of 3 to 15 A/dm2 in a silver plating solution so as to satisfy (32.6x?300)?y?(32.6x+200) assuming that a product of a concentration of potassium cyanide in the silver plating solution and a current density is y (g·A/L·dm2) and that a liquid temperature of the silver plating solution is x (° C.), the silver plating solution containing 80 to 110 g/L of silver, 70 to 160 g/L of potassium cyanide and 55 to 70 mg/L of selenium.

Abstract: A high electron mobility field effect transistor (HEMT) having a substrate, a channel layer on the substrate and a barrier layer on the channel layer includes a stress inducing layer on the barrier layer, the stress inducing layer varying a piezo-electric effect in the barrier layer in a drift region between a gate and a drain, wherein a two dimensional electron gas (2DEG) has a non-uniform lateral distribution in the drift region between the gate and the drain, wherein the stress inducing layer comprises a material having a height that decreases linearly and monotonically in the drift region in the direction from the gate towards the drain, and wherein the 2DEG decreases in density in the drift region between the gate and the drain.

Abstract: An iron rivet including a head and a shank, an aluminum plate, an iron plate, and first and second electrodes are prepared. A sandwiching step of sandwiching the rivet, the aluminum plate, and the iron plate between the first electrode and the second electrode, a penetration step of performing pressurization and current application by the first and second electrodes so that the shank penetrates through the aluminum plate, and a forming step of performing pressurization and current application by the first and second electrodes so that a nugget is formed between the shank and the iron plate are included. In the penetration step, the pressurization and current application is performed while air is blown to a side face of the shank so that the air hits a region around a boundary between the shank and the aluminum plate.

Abstract: A silver-plated product, wherein the preferred orientation plane of a surface layer of silver is {111} plane and wherein the ratio of the full-width at half maximum of an X-ray diffraction peak on {111} plane after heating the silver-plated product at 50° C. for 168 hours to the full-width at half maximum of an X-ray diffraction peak on {111} plane before the heating of the silver-plated product is not less than 0.5, is produced by forming the surface layer on a base material by electroplating at a liquid temperature of 12 to 24° C. and a current density of 3 to 8 A/dm2 in a silver plating solution which contains 80 to 110 g/L of silver, 70 to 160 g/L of potassium cyanide and 55 to 70 mg/L of selenium, so as to cause the product of the concentration of potassium cyanide and the current density to be 840 g·A/L·dm2 or less.

Abstract: A silver-plated product is produced by forming a surface layer of silver on a base material by electroplating at a liquid temperature of 10 to 35° C. and a current density of 3 to 15 A/dm2 in a silver plating solution so as to satisfy (32.6x?300)?y?(32.6x+200) assuming that a product of a concentration of potassium cyanide in the silver plating solution and a current density is y (g·A/L·dm2) and that a liquid temperature of the silver plating solution is x (° C.), the silver plating solution containing 80 to 110 g/L of silver, 70 to 160 g/L of potassium cyanide and 55 to 70 mg/L of selenium.

Abstract: A silver-plated product is produced by forming a surface layer of silver on a base material by electroplating at a liquid temperature of 10 to 35° C. and a current density of 3 to 15 A/dm2 in a silver plating solution so as to satisfy (32.6x?300)?y?(32.6x+200) assuming that a product of a concentration of potassium cyanide in the silver plating solution and a current density is y (g·A/L·dm2) and that a liquid temperature of the silver plating solution is x (° C.), the silver plating solution containing 80 to 110 g/L of silver, 70 to 160 g/L of potassium cyanide and 55 to 70 mg/L of selenium.

Abstract: A monolithically integrated device includes a substrate, a first set of Group III nitride epitaxial layers grown for a first HFET on a first region of the substrate, and a second set of Group III nitride epitaxial layers for a second HFET grown on a second region of the substrate.

Abstract: A FET with a buried gate structure. The FET's gate electrode comprises a plurality of buried gate structures, the tops of which extend above the substrate's top surface and the bottoms of which are buried to a depth at least equal to that of the bottom of the channel layer, or the 2DEG plane within a channel layer for a HEMT, such that the buried gate structures contact the channel layer only from its sides. A head portion above and not in contact with the substrate's top surface contacts the tops of and interconnects all of the buried gate structures. Drain current is controlled by channel width modulation by lateral gating of the channel layer by the buried gates structures. The FET may include at least one field plate which comprises a slit structure in which the field plate is divided into segments.

Abstract: A FET employing a micro-scale device array structure comprises a substrate on which an epitaxial active channel area has been grown, with a plurality of micro-cells uniformly distributed over the active channel area. Each micro-cell comprises a source electrode, a drain electrode, and at least one gate electrode, with a first metal layer interconnecting either the drain or the source electrodes, a second metal layer interconnecting the gate electrodes, and a third metal layer interconnecting the other of the drain or source electrodes. Each micro-cell preferably comprises a source or drain electrode at the center of the micro-cell, with the corresponding drain or source electrode surrounding the center electrode. The number and width of the gate electrodes in each micro-cell may be selected to achieve a desired power density and/or heat distribution, and/or to minimize the FET's junction temperature. The FET structure may be used to form, for example, HEMTs or MESFETs.

Abstract: Methods using chemical vapor deposition (CVD) of diamond deposited on a sacrificial material provide CVD diamond microchannel structures and 3-D interconnection structures of CVD diamond microfluidic channels. The sacrificial material is patterned to define locations and dimensions of the microchannels. The patterned sacrificial material is selectively removed from underneath the chemical vapor deposited (CVD) diamond to form the CVD diamond microchannels. The CVD diamond microchannels are integrated with electronic structures to provide an integral microfluidic cooling system to electronic devices.

Abstract: A high electron mobility field effect transistor (HEMT) having a substrate, a channel layer on the substrate and a barrier layer on the channel layer includes a stress inducing layer on the barrier layer, the stress inducing layer varying the piezo-electric effect in the barrier layer in a drift region between a gate and a drain. A two dimensional electron gas (2DEG) has a non-uniform lateral distribution in the drift region between the gate and the drain.

Abstract: A FET with a buried gate structure. The FET's gate electrode comprises a plurality of buried gate structures, the tops of which extend above the substrate's top surface and the bottoms of which are buried to a depth at least equal to that of the bottom of the channel layer, or the 2DEG plane within a channel layer for a HEMT, such that the buried gate structures contact the channel layer only from its sides. A head portion above and not in contact with the substrate's top surface contacts the tops of and interconnects all of the buried gate structures. Drain current is controlled by channel width modulation by lateral gating of the channel layer by the buried gates structures. The FET may include at least one field plate which comprises a slit structure in which the field plate is divided into segments.

Abstract: A FET employing a micro-scale device array structure comprises a substrate on which an epitaxial active channel area has been grown, with a plurality of micro-cells uniformly distributed over the active channel area. Each micro-cell comprises a source electrode, a drain electrode, and at least one gate electrode, with a first metal layer interconnecting either the drain or the source electrodes, a second metal layer interconnecting the gate electrodes, and a third metal layer interconnecting the other of the drain or source electrodes. Each micro-cell preferably comprises a source or drain electrode at the center of the micro-cell, with the corresponding drain or source electrode surrounding the center electrode. The number and width of the gate electrodes in each micro-cell may be selected to achieve a desired power density and/or heat distribution, and/or to minimize the FET's junction temperature. The FET structure may be used to form, for example, HEMTs or MESFETs.

Abstract: Semiconductor devices, such as transistors, FETs and HEMTs having a non-linear gate foot region and non-linear channel width are disclosed as well as methods of making and using such devices and the operational benefits of the devices.