Abstract: A high electron mobility field effect transistor (HEMT) having a substrate, a channel layer on the substrate and a barrier layer on the channel layer includes a stress inducing layer on the barrier layer, the stress inducing layer varying a piezo-electric effect in the barrier layer in a drift region between a gate and a drain, wherein a two dimensional electron gas (2DEG) has a non-uniform lateral distribution in the drift region between the gate and the drain, wherein the stress inducing layer comprises a material having a height that decreases linearly and monotonically in the drift region in the direction from the gate towards the drain, and wherein the 2DEG decreases in density in the drift region between the gate and the drain.

Abstract: There is provided a silver-plated product which has good thermal resistance, bendability and wear resistance. In a silver-plated product wherein a surface layer of silver having a thickness of 10 ?m or less is formed on a base material of copper or a copper alloy, the full-width at half maximum of a rocking curve on a preferred orientation plane (preferably {200} or {111} plane) of the surface layer is caused to be 2 to 8°, preferably 3 to 7°, to improve the out-of-plane orientation of the surface layer to improve the thermal resistance, bendability and wear resistance of the silver-plated product.

Abstract: There is provided a silver-plated product wherein a surface layer of silver is formed on the surface of an underlying layer of nickel formed on a base material, the silver-plated product having a good bendability. In a silver-plated product which comprises a base material of copper or a copper alloy, an underlying layer of nickel formed on the base material, and a surface layer of silver formed on the surface of the underlying layer, the surface layer having a thickness of 10 ?m or less, the thickness of the underlying layer is 2 ?m or less, preferably 1.5 ?m or less, and the area fraction in {200} orientation of the surface layer is 15% or more, preferably 25% or more.

Abstract: An electronic circuit comprising: an integrated circuit chip, the integrated circuit chip having a top face; portions of the top face of the chip being covered by a first metal layer electrically connected to the integrated circuit; and a dialectic layer formed on the top face of the chip beside and on top of said first metal layer; wherein the dielectric layer extends parallel to the top face of the chip beyond the edges of the chip, the first metal layer extending in the dielectric layer beyond the edges of the chip; and wherein portions of a top surface of the dielectric layer are covered by a second metal layer, portions of the first and second metal layers being electrically connected through the dielectric layer.

Abstract: A monolithically integrated device includes a substrate, a first set of Group III nitride epitaxial layers grown for a first HFET on a first region of the substrate, and a second set of Group III nitride epitaxial layers for a second HFET grown on a second region of the substrate.

Abstract: A method of making a stepped field gate for an FET including forming a first passivation layer on a barrier layer, defining a first field plate by using electron beam (EB) lithography and by depositing a first negative EB resist, forming a second passivation layer over first negative EB resist and the first passivation layer, planarizing the first negative EB resist and the second passivation layer, defining a second field plate by using EB lithography and by depositing a second negative EB resist connected to the first negative EB resist, forming a third passivation layer over second negative EB resist and the second passivation layer, planarizing the second negative EB resist and the third passivation layer, removing the first and second negative EB resist, and forming a stepped field gate by using lithography and plating in a void left by the removed first and second negative EB resist.

Abstract: There is provided a silver-plated product wherein a silver plating film having a thickness of not greater than 10 micrometers is formed on a base material of copper or a copper alloy and wherein the surface of the silver plating film has an arithmetic average roughness Ra of not greater than 0.1 micrometers, and the silver plating film has a {111} orientation ratio of not less than 35%.

Abstract: A silver-plated product is produced by forming a surface layer of silver on a base material by electroplating at a liquid temperature of 10 to 35° C. and a current density of 3 to 15 A/dm2 in a silver plating solution so as to satisfy (32.6x?300)?y?(32.6x+200) assuming that a product of a concentration of potassium cyanide in the silver plating solution and a current density is y (g·A/L·dm2) and that a liquid temperature of the silver plating solution is x (° C.), the silver plating solution containing 80 to 110 g/L of silver, 70 to 160 g/L of potassium cyanide and 55 to 70 mg/L of selenium.

Abstract: A compound semiconductor integrated circuit comprising a first substrate; a first electronic component formed on top of said first substrate; a layer of a first dielectric material formed on top of said first substrate and including said first electronic component, said layer of a first dielectric material comprising a recess exposing a first region of said first substrate; and a layer of a second dielectric material attached to said first substrate on top of said first region of said first substrate after manufacturing of said layer of a second dielectric material, said layer of a second material comprising a second electronic component.

Abstract: There is provided a silver-plated product which has a good bendability and which can restrain the rise of the contact resistance thereof even if it is used in a high-temperature environment, and a method for producing the same. In a silver-plated product wherein a surface layer of silver is formed on the surface of a base material of copper or a copper alloy, or on the surface of an underlying layer of copper or a copper alloy formed on the base material, the percentage of an X-ray diffraction intensity on {200} plane of the surface layer with respect to the sum of X-ray diffraction intensities on {111}, {200}, {220} and {311} planes of the surface layer is 40% or more.

Abstract: In a silver-plated product wherein a surface layer of silver is formed on the surface of a base material or on the surface of an underlying layer formed on the base material, the surface layer of silver is formed by electroplating in a silver plating bath which contains 1 to 15 mg/L of selenium and wherein a mass ratio of silver to free cyanogen is in the range of from 0.9 to 1.8, and thereafter, an aging treatment is carried out to produce a silver-plated product wherein an area fraction in {200} orientation of the surface layer is 15% or more.

Abstract: An electronic circuit comprising: an integrated circuit chip, the integrated circuit chip having a top face; portions of the top face of the chip being covered by a first metal layer electrically connected to the integrated circuit; and a dielectic layer formed on the top face of the chip beside and on top of said first metal layer; wherein the dielectric layer extends parallel to the top face of the chip beyond the edges of the chip, the first metal layer extending in the dielectric layer beyond the edges of the chip; and wherein portions of a top surface of the dielectric layer are covered by a second metal layer, portions of the first and second metal layers being electrically connected through the dielectric layer.

Abstract: Monolithic integration of high-frequency GaN-HEMTs and GaN-Schottky diodes. The integrated HEMTs/Schottky diodes are realized using an epitaxial structure and a fabrication process which reduces fabrication cost. Since the disclosed process preferably uses self-aligned technology, both devices show extremely high-frequency performance by minimizing device parasitic resistances and capacitances. Furthermore, since the Schottky contact of diodes is formed by making a direct contact of an anode metal to the 2DEG channel the resulting structure minimizes an intrinsic junction capacitance due to the very thin contact area size. The low resistance of high-mobility 2DEG channel and a low contact resistance realized by a n+GaN ohmic regrowth layer reduce a series resistance of diodes as well as access resistance of the HEMT.

Abstract: A compound semiconductor integrated circuit comprising a first substrate; a first electronic component formed on top of said first substrate; a layer of a first dielectric material formed on top of said first substrate and including said first electronic component, said layer of a first dielectric material comprising a recess exposing a first region of said first substrate; and a layer of a second dielectric material attached to said first substrate on top of said first region of said first substrate after manufacturing of said layer of a second dielectric material, said layer of a second material comprising a second electronic component.

Abstract: Apparatus and methods are provided for heat removal and spreading from a field effect transistor (FET) including a substrate, a first source, a first gate, and a drain on the substrate, and a poly-diamond dielectric thermally coupled to the first gate wherein the poly-diamond dielectric facilitates heat removal from a top of the FET.

Abstract: There is provided a silver-plated product which has good thermal resistance, bendability and wear resistance. In a silver-plated product wherein a surface layer of silver having a thickness of 10 ?m or less is formed on a base material of copper or a copper alloy, the full-width at half maximum of a rocking curve on a preferred orientation plane (preferably {200} or {111} plane) of the surface layer is caused to be 2 to 8°, preferably 3 to 7°, to improve the out-of-plane orientation of the surface layer to improve the thermal resistance, bendability and wear resistance of the silver-plated product.

Abstract: There is provided a silver-plated product wherein a surface layer of silver is formed on the surface of an underlying layer of nickel formed on a base material, the silver-plated product having a good bendability. In a silver-plated product which comprises a base material of copper or a copper alloy, an underlying layer of nickel formed on the base material, and a surface layer of silver formed on the surface of the underlying layer, the surface layer having a thickness of 10 ?m or less, the thickness of the underlying layer is 2 ?m or less, preferably 1.5 ?m or less, and the area fraction in {200} orientation of the surface layer is 15% or more, preferably 25% or more.

Abstract: A self-aligned process for locating a stem of a T-shaped gate relative to source and drain contacts of a FET or HEMT. The gate stem is located asymmetrically in some embodiments and in such embodiments the stem of the T-shaped gate is located relative to drain and source contacts of the device by forming a plurality of sidewall spacers, with more sidewall spacers being formed on the drain side of the stem than are formed on the source side of the stem. Additionally the gate stem preferably has a high aspect ratio to improve the performance of the resulting FET or HEMT. Drain and source contacts are preferably formed of an n+ semiconductor material.

Abstract: A silver-plated product, wherein the preferred orientation plane of a surface layer of silver is {111} plane and wherein the ratio of the full-width at half maximum of an X-ray diffraction peak on {111} plane after heating the silver-plated product at 50° C. for 168 hours to the full-width at half maximum of an X-ray diffraction peak on {111} plane before the heating of the silver-plated product is not less than 0.5, is produced by forming the surface layer on a base material by electroplating at a liquid temperature of 12 to 24° C. and a current density of 3 to 8 A/dm2 in a silver plating solution which contains 80 to 110 g/L of silver, 70 to 160 g/L of potassium cyanide and 55 to 70 mg/L of selenium, so as to cause the product of the concentration of potassium cyanide and the current density to be 840 g·A/L·dm2 or less.

Abstract: A method of making a stepped field gate for an FET including forming a first set of layers having a passivation layer on a barrier layer of the FET and a first etch stop layer over the first passivation layer, forming additional sets of layers having alternating passivation layer and etch stop layers, successively removing portions of each set of layers using lithography and reactive ion etching to form stepped passivation layers and a gate foot, applying a mask having an opening defining an extent of a stepped field-plate gate, and forming the stepped field plate gate and the gate foot by plating through the opening in the mask.