Patents by Inventor Keitaro Imai

Keitaro Imai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230387318
    Abstract: An objet of the present invention is to provide a semiconductor device with a new structure. Disclosed is a semiconductor device including a first transistor which includes a channel formation region on a substrate containing a semiconductor material, impurity regions formed with the channel formation region interposed therebetween, a first gate insulating layer over the channel formation region, a first gate electrode over the first gate insulating layer, and a first source electrode and a first drain electrode which are electrically connected to the impurity region; and a second transistor which includes a second gate electrode over the substrate containing a semiconductor material, a second gate insulating layer over the second gate electrode, an oxide semiconductor layer over the second gate insulating layer, and a second source electrode and a second drain electrode which are electrically connected to the oxide semiconductor layer.
    Type: Application
    Filed: August 14, 2023
    Publication date: November 30, 2023
    Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Keitaro IMAI
  • Publication number: 20230369510
    Abstract: An objet of the present invention is to provide a semiconductor device with a new structure. Disclosed is a semiconductor device including a first transistor which includes a channel formation region on a substrate containing a semiconductor material, impurity regions formed with the channel formation region interposed therebetween, a first gate insulating layer over the channel formation region, a first gate electrode over the first gate insulating layer, and a first source electrode and a first drain electrode which are electrically connected to the impurity region; and a second transistor which includes a second gate electrode over the substrate containing a semiconductor material, a second gate insulating layer over the second gate electrode, an oxide semiconductor layer over the second gate insulating layer, and a second source electrode and a second drain electrode which are electrically connected to the oxide semiconductor layer.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 16, 2023
    Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Keitaro IMAI
  • Publication number: 20210305432
    Abstract: An objet of the present invention is to provide a semiconductor device with a new structure. Disclosed is a semiconductor device including a first transistor which includes a channel formation region on a substrate containing a semiconductor material, impurity regions formed with the channel formation region interposed therebetween, a first gate insulating layer over the channel formation region, a first gate electrode over the first gate insulating layer, and a first source electrode and a first drain electrode which are electrically connected to the impurity region; and a second transistor which includes a second gate electrode over the substrate containing a semiconductor material, a second gate insulating layer over the second gate electrode, an oxide semiconductor layer over the second gate insulating layer, and a second source electrode and a second drain electrode which are electrically connected to the oxide semiconductor layer.
    Type: Application
    Filed: June 11, 2021
    Publication date: September 30, 2021
    Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Keitaro IMAI
  • Patent number: 10720433
    Abstract: The semiconductor device includes: a transistor having an oxide semiconductor layer; and a logic circuit formed using a semiconductor material other than an oxide semiconductor. One of a source electrode and a drain electrode of the transistor is electrically connected to at least one input of the logic circuit, and at least one input signal is applied to the logic circuit through the transistor. The off-current of the transistor is preferably 1×10?13 A or less.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: July 21, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Keitaro Imai, Jun Koyama
  • Patent number: 10522689
    Abstract: It is an object to manufacture a semiconductor device in which a transistor including an oxide semiconductor has normally-off characteristics, small fluctuation in electric characteristics, and high reliability. First, first heat treatment is performed on a substrate, a base insulating layer is formed over the substrate, an oxide semiconductor layer is formed over the base insulating layer, and the step of performing the first heat treatment to the step of forming the oxide semiconductor layer are performed without exposure to the air. Next, after the oxide semiconductor layer is formed, second heat treatment is performed. An insulating layer from which oxygen is released by heating is used as the base insulating layer.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: December 31, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshinari Sasaki, Hitomi Sato, Kosei Noda, Yuta Endo, Mizuho Ikarashi, Keitaro Imai, Atsuo Isobe, Yutaka Okazaki
  • Publication number: 20180047730
    Abstract: The semiconductor device includes: a transistor having an oxide semiconductor layer; and a logic circuit formed using a semiconductor material other than an oxide semiconductor. One of a source electrode and a drain electrode of the transistor is electrically connected to at least one input of the logic circuit, and at least one input signal is applied to the logic circuit through the transistor. The off-current of the transistor is preferably 1×10?13 A or less.
    Type: Application
    Filed: October 10, 2017
    Publication date: February 15, 2018
    Inventors: Shunpei YAMAZAKI, Keitaro IMAI, Jun KOYAMA
  • Patent number: 9806079
    Abstract: The semiconductor device includes: a transistor having an oxide semiconductor layer; and a logic circuit formed using a semiconductor material other than an oxide semiconductor. One of a source electrode and a drain electrode of the transistor is electrically connected to at least one input of the logic circuit, and at least one input signal is applied to the logic circuit through the transistor. The off-current of the transistor is preferably 1×10?13 A or less.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: October 31, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Keitaro Imai, Jun Koyama
  • Publication number: 20170271519
    Abstract: It is an object to manufacture a semiconductor device in which a transistor including an oxide semiconductor has normally-off characteristics, small fluctuation in electric characteristics, and high reliability. First, first heat treatment is performed on a substrate, a base insulating layer is formed over the substrate, an oxide semiconductor layer is formed over the base insulating layer, and the step of performing the first heat treatment to the step of forming the oxide semiconductor layer are performed without exposure to the air. Next, after the oxide semiconductor layer is formed, second heat treatment is performed. An insulating layer from which oxygen is released by heating is used as the base insulating layer.
    Type: Application
    Filed: May 25, 2017
    Publication date: September 21, 2017
    Inventors: Toshinari SASAKI, Hitomi SATO, Kosei NODA, Yuta ENDO, Mizuho IKARASHI, Keitaro IMAI, Atsuo ISOBE, Yutaka OKAZAKI
  • Patent number: 9666720
    Abstract: It is an object to manufacture a semiconductor device in which a transistor including an oxide semiconductor has normally-off characteristics, small fluctuation in electric characteristics, and high reliability. First, first heat treatment is performed on a substrate, a base insulating layer is formed over the substrate, an oxide semiconductor layer is formed over the base insulating layer, and the step of performing the first heat treatment to the step of forming the oxide semiconductor layer are performed without exposure to the air. Next, after the oxide semiconductor layer is formed, second heat treatment is performed. An insulating layer from which oxygen is released by heating is used as the base insulating layer.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: May 30, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshinari Sasaki, Hitomi Sato, Kosei Noda, Yuta Endo, Mizuho Ikarashi, Keitaro Imai, Atsuo Isobe, Yutaka Okazaki
  • Publication number: 20160079245
    Abstract: The semiconductor device includes: a transistor having an oxide semiconductor layer; and a logic circuit formed using a semiconductor material other than an oxide semiconductor. One of a source electrode and a drain electrode of the transistor is electrically connected to at least one input of the logic circuit, and at least one input signal is applied to the logic circuit through the transistor. The off-current of the transistor is preferably 1×10?13 A or less.
    Type: Application
    Filed: November 24, 2015
    Publication date: March 17, 2016
    Inventors: Shunpei YAMAZAKI, Keitaro IMAI, Jun KOYAMA
  • Patent number: 9287343
    Abstract: It is an object of the present invention to provide a display device preventing the external invasion of water and/or oxygen and preventing the deterioration of a luminous element due to these invading substances and to provide a production method including simple production steps for producing the display device. The invention provides a display device having a sealing material on the rim of an exposed interlayer insulator for preventing the invasion of water and/or oxygen from the interlayer insulator. Further, the invention provides a display device having a barrier body on an exposed interlayer insulator for preventing the invasion of water and/or oxygen from the interlayer insulator. Furthermore, the application of droplet discharge technique in production steps for producing the display device can eliminate a photolithography step such as exposing and developing. Thus, a method of producing a display device having an improved yield is provided.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: March 15, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Keitaro Imai, Aya Anzai, Yasuko Watanabe
  • Patent number: 9202546
    Abstract: The semiconductor device includes: a transistor having an oxide semiconductor layer; and a logic circuit formed using a semiconductor material other than an oxide semiconductor. One of a source electrode and a drain electrode of the transistor is electrically connected to at least one input of the logic circuit, and at least one input signal is applied to the logic circuit through the transistor. The off-current of the transistor is preferably 1×10?13 A or less.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: December 1, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Keitaro Imai, Jun Koyama
  • Publication number: 20150137154
    Abstract: It is an object of the present invention to provide a display device preventing the external invasion of water and/or oxygen and preventing the deterioration of a luminous element due to these invading substances and to provide a production method including simple production steps for producing the display device. The invention provides a display device having a sealing material on the rim of an exposed interlayer insulator for preventing the invasion of water and/or oxygen from the interlayer insulator. Further, the invention provides a display device having a barrier body on an exposed interlayer insulator for preventing the invasion of water and/or oxygen from the interlayer insulator. Furthermore, the application of droplet discharge technique in production steps for producing the display device can eliminate a photolithography step such as exposing and developing. Thus, a method of producing a display device having an improved yield is provided.
    Type: Application
    Filed: January 29, 2015
    Publication date: May 21, 2015
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Keitaro IMAI, Aya ANZAI, Yasuko WATANABE
  • Patent number: 8987068
    Abstract: At least one or more of a conductive layer which forms a wiring or an electrode and a pattern necessary for manufacturing a display panel such as a mask for forming a predetermined pattern is formed by a method capable of selectively forming a pattern to manufacture a liquid crystal display device. A droplet discharge method capable of forming a predetermined pattern by selectively discharging a droplet of a composition in accordance with a particular object is used as a method capable of selectively forming a pattern in forming a conductive layer, an insulating layer, or the like.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: March 24, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Shinji Maekawa, Makoto Furuno, Osamu Nakamura, Keitaro Imai
  • Patent number: 8946988
    Abstract: It is an object of the present invention to provide a display device preventing the external invasion of water and/or oxygen and preventing the deterioration of a luminous element due to these invading substances and to provide a production method including simple production steps for producing the display device. The invention provides a display device having a sealing material on the rim of an exposed interlayer insulator for preventing the invasion of water and/or oxygen from the interlayer insulator. Further, the invention provides a display device having a barrier body on an exposed interlayer insulator for preventing the invasion of water and/or oxygen from the interlayer insulator. Furthermore, the application of droplet discharge technique in production steps for producing the display device can eliminate a photolithography step such as exposing and developing. Thus, a method of producing a display device having an improved yield is provided.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: February 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Keitaro Imai, Aya Anzai, Yasuko Watanabe
  • Publication number: 20140306224
    Abstract: It is an object of the present invention to provide a display device preventing the external invasion of water and/or oxygen and preventing the deterioration of a luminous element due to these invading substances and to provide a production method including simple production steps for producing the display device. The invention provides a display device having a sealing material on the rim of an exposed interlayer insulator for preventing the invasion of water and/or oxygen from the interlayer insulator. Further, the invention provides a display device having a barrier body on an exposed interlayer insulator for preventing the invasion of water and/or oxygen from the interlayer insulator. Furthermore, the application of droplet discharge technique in production steps for producing the display device can eliminate a photolithography step such as exposing and developing. Thus, a method of producing a display device having an improved yield is provided.
    Type: Application
    Filed: June 2, 2014
    Publication date: October 16, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Keitaro Imai, Aya Anzai, Yasuko Watanabe
  • Publication number: 20140239297
    Abstract: It is an object to manufacture a semiconductor device in which a transistor including an oxide semiconductor has normally-off characteristics, small fluctuation in electric characteristics, and high reliability. First, first heat treatment is performed on a substrate, a base insulating layer is formed over the substrate, an oxide semiconductor layer is formed over the base insulating layer, and the step of performing the first heat treatment to the step of forming the oxide semiconductor layer are performed without exposure to the air. Next, after the oxide semiconductor layer is formed, second heat treatment is performed. An insulating layer from which oxygen is released by heating is used as the base insulating layer.
    Type: Application
    Filed: May 5, 2014
    Publication date: August 28, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshinari SASAKI, Hitomi SATO, Kosei NODA, Yuta ENDO, Mizuho IKARASHI, Keitaro IMAI, Atsuo ISOBE, Yutaka OKAZAKI
  • Patent number: 8760594
    Abstract: Conventionally, photolithography and anisotropic etching are performed to form a plug between an electrode and a wiring, etc., thereby increasing the number of steps, getting the throughput worse, and producing unnecessary materials. To solve the problems, the present invention provides a method for manufacturing a display device, including the formation steps of a conductive layer or wirings, and a contact plug that can treat a larger substrate. In the case of forming a plug for electrically connecting conductive patterns comprising plural layers, a pillar made of a conductor is formed over a base conductive layer pattern, and then, after an insulating film is formed over the entire surface, the insulating film is etched back to expose the conductor pillar, and a conductive pattern in an upper layer is formed by ink jetting. In this case, when the conductor pillar is processed, a resist to be a mask can be formed in itself by ink jetting.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: June 24, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Keitaro Imai
  • Publication number: 20140167041
    Abstract: An objet of the present invention is to provide a semiconductor device with a new structure. Disclosed is a semiconductor device including a first transistor which includes a channel formation region on a substrate containing a semiconductor material, impurity regions formed with the channel formation region interposed therebetween, a first gate insulating layer over the channel formation region, a first gate electrode over the first gate insulating layer, and a first source electrode and a first drain electrode which are electrically connected to the impurity region; and a second transistor which includes a second gate electrode over the substrate containing a semiconductor material, a second gate insulating layer over the second gate electrode, an oxide semiconductor layer over the second gate insulating layer, and a second source electrode and a second drain electrode which are electrically connected to the oxide semiconductor layer.
    Type: Application
    Filed: February 24, 2014
    Publication date: June 19, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Keitaro IMAI
  • Patent number: 8748889
    Abstract: It is an object to manufacture a semiconductor device in which a transistor including an oxide semiconductor has normally-off characteristics, small fluctuation in electric characteristics, and high reliability. First, first heat treatment is performed on a substrate, a base insulating layer is formed over the substrate, an oxide semiconductor layer is formed over the base insulating layer, and the step of performing the first heat treatment to the step of forming the oxide semiconductor layer are performed without exposure to the air. Next, after the oxide semiconductor layer is formed, second heat treatment is performed. An insulating layer from which oxygen is released by heating is used as the base insulating layer.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: June 10, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshinari Sasaki, Hitomi Sato, Kosei Noda, Yuta Endo, Mizuho Ikarashi, Keitaro Imai, Atsuo Isobe, Yutaka Okazaki