Patents by Inventor Kelin J. Kuhn

Kelin J. Kuhn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120138886
    Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.
    Type: Application
    Filed: December 1, 2010
    Publication date: June 7, 2012
    Inventors: Kelin J. Kuhn, Seiyon Kim, Rafael Rios, Stephen M. Cea, Martin D. Giles, Annalisa Cappellani, Titash Rakshit, Peter Chang, Willy Rachmady
  • Publication number: 20120074464
    Abstract: A method and a device made according to the method. The method comprises providing a substrate including a first material, and providing a fin including a second material, the fin being disposed on the substrate and having a device active portion, the first material and the second material presenting a lattice mismatch between respective crystalline structures thereof. Providing the fin includes providing a biaxially strained film including the second material on the substrate; and removing parts of the biaxially strained film to form a substantially uniaxially strained fin therefrom.
    Type: Application
    Filed: September 23, 2010
    Publication date: March 29, 2012
    Inventors: Stephen M. Cea, Roza Kotlyar, Jack T. Kavalieros, Martin D. Giles, Tahir Ghani, Kelin J. Kuhn, Markus Kuhn, Nancy M. Zelick
  • Patent number: 7999607
    Abstract: Power switch units for microelectronic devices are disclosed. In one aspect, a microelectronic device may include a functional circuit, and a power switch unit to switch power to the functional circuit on and off. The power switch unit may include a large number of transistors coupled together. The transistors may include predominantly positive-channel, insulated gate field effect transistors, which have a gate dielectric that includes a high dielectric constant material. Power switch units having such transistors may tend to have low power consumption. In an aspect, an overdrive voltage may be applied to the gates of such transistors to further reduce power consumption. Methods of overdriving such transistors and systems including such power switch units are also disclosed.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: August 16, 2011
    Assignee: Intel Corporation
    Inventors: Kelin J. Kuhn, Richard K. Hose, Jr., Edward Burton, Rajesh Kumar
  • Publication number: 20110147848
    Abstract: The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to forming transistor fins of differing heights to obtain a performance improvement for a given type of integrated circuit within the microelectronic device.
    Type: Application
    Filed: December 23, 2009
    Publication date: June 23, 2011
    Inventors: Kelin J. Kuhn, Tahir Ghani, Justin S. Sandford
  • Patent number: 7888710
    Abstract: Complementary metal oxide semiconductor transistors are formed on a silicon substrate. The substrate has a {100} crystallographic orientation. The transistors are formed on the substrate so that current flows in the channels of the transistors are parallel to the <100> direction. Additionally, longitudinal tensile stress is applied to the channels.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: February 15, 2011
    Assignee: Intel Corporation
    Inventors: Mark Armstrong, Gerhard Schrom, Sunit Tyagi, Paul A. Packan, Kelin J. Kuhn, Scott Thompson
  • Publication number: 20100214005
    Abstract: Power switch units for microelectronic devices are disclosed. In one aspect, a microelectronic device may include a functional circuit, and a power switch unit to switch power to the functional circuit on and off. The power switch unit may include a large number of transistors coupled together. The transistors may include predominantly positive-channel, insulated gate field effect transistors, which have a gate dielectric that includes a high dielectric constant material. Power switch units having such transistors may tend to have low power consumption. In an aspect, an overdrive voltage may be applied to the gates of such transistors to further reduce power consumption. Methods of overdriving such transistors and systems including such power switch units are also disclosed.
    Type: Application
    Filed: May 6, 2010
    Publication date: August 26, 2010
    Inventors: Kelin J. Kuhn, Richard K. Hose, JR., Edward Burton, Rajesh Kumar
  • Patent number: 7737770
    Abstract: Power switch units for microelectronic devices are disclosed. In one aspect, a microelectronic device may include a functional circuit, and a power switch unit to switch power to the functional circuit on and off. The power switch unit may include a large number of transistors coupled together. The transistors may include predominantly positive-channel, insulated gate field effect transistors, which have a gate dielectric that includes a high dielectric constant material. Power switch units having such transistors may tend to have low power consumption. In an aspect, an overdrive voltage may be applied to the gates of such transistors to further reduce power consumption. Methods of overdriving such transistors and systems including such power switch units are also disclosed.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: June 15, 2010
    Assignee: Intel Corporation
    Inventors: Kelin J. Kuhn, Richard K. Hose, Jr., Edward Burton, Rajesh Kumar
  • Publication number: 20090057774
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may comprise forming an opening in a masking layer, implanting an amorphizing species into a silicon region disposed within the opening, wherein the silicon region comprises a portion of an emitter of a bipolar transistor; and forming a silicide layer on the silicon region.
    Type: Application
    Filed: October 24, 2008
    Publication date: March 5, 2009
    Inventors: Kelin J. Kuhn, Bo Zheng
  • Publication number: 20070298576
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may comprise forming an opening in a masking layer, implanting an amorphizing species into a silicon region disposed within the opening, wherein the silicon region comprises a portion of an emitter of a bipolar transistor; and forming a silicide layer on the silicon region.
    Type: Application
    Filed: June 21, 2006
    Publication date: December 27, 2007
    Inventors: Kelin J. Kuhn, Bo Zheng
  • Patent number: 7312485
    Abstract: Complementary metal oxide semiconductor transistors are formed on a silicon substrate. The substrate has a {100} crystallographic orientation. The transistors are formed on the substrate so that current flows in the channels of the transistors are parallel to the <100> direction. Additionally, longitudinal tensile stress is applied to the channels.
    Type: Grant
    Filed: November 29, 2000
    Date of Patent: December 25, 2007
    Assignee: Intel Corporation
    Inventors: Mark Armstrong, Gerhard Schrom, Sunit Tyagi, Paul A. Packan, Kelin J. Kuhn, Scott Thompson
  • Publication number: 20070273042
    Abstract: Methods of fabricating a first contact to a semiconductor device, which fundamentally comprises providing a semiconductor device formed on a substrate. The substrate further includes a conductive surface. A dielectric layer is formed over the substrate and has an opening exposing the conductive surface. The opening extends an entire length of the semiconductor device, partway down the entire length of the device, extending from the device onto adjacent field of the device, or and a combination thereof. A barrier layer is formed within the opening. A copper containing material fills the opening to form a first contact to the semiconductor device.
    Type: Application
    Filed: May 23, 2006
    Publication date: November 29, 2007
    Inventors: Kelin J. Kuhn, Kaizad Mistry, Mark Bohr, Chris Auth
  • Patent number: 6627506
    Abstract: The present invention relates to a method of forming an isolation trench that comprises forming a recess in a substrate and forming a film upon the sidewall under conditions that cause the film to have a tensile load. The method includes filling the recess with a material that imparts a compressive load upon the film under conditions that oppose the tensile load. The present invention is particularly well suited for shallow isolation trench filling in the 0.13 micron geometry range, and smaller.
    Type: Grant
    Filed: July 18, 2001
    Date of Patent: September 30, 2003
    Assignee: Intel Corporation
    Inventors: Kelin J. Kuhn, Ian R. Post
  • Publication number: 20020063292
    Abstract: Complementary metal oxide semiconductor transistors are formed on a silicon substrate. The substrate has a {100} crystallographic orientation. The transistors are formed on the substrate so that current flows in the channels of the transistors are parallel to the <100>direction. Additionally, longitudinal tensile stress is applied to the channels.
    Type: Application
    Filed: November 29, 2000
    Publication date: May 30, 2002
    Inventors: Mark Armstrong, Gerhard Schrom, Sunit Tyagi, Paul A. Packan, Kelin J. Kuhn, Scott Thompson
  • Publication number: 20020045325
    Abstract: The present invention relates to a method of forming an isolation trench that comprises forming a recess in a substrate and forming a film upon the sidewall under conditions that cause the film to have a tensile load. The method includes filling the recess with a material that imparts a compressive load upon the film under conditions that oppose the tensile load. The present invention is particularly well suited for shallow isolation trench filling in the 0.13 micron geometry range, and smaller.
    Type: Application
    Filed: July 18, 2001
    Publication date: April 18, 2002
    Applicant: Intel Corporation
    Inventors: Kelin J. Kuhn, Ian R. Post
  • Patent number: 6368931
    Abstract: The present invention relates to a method of forming an isolation trench that comprises forming a recess in a substrate and forming a film upon the sidewall under conditions that cause the film to have a tensile load. The method includes filling the recess with a material that imparts a compressive load upon the film under conditions that oppose the tensile load. The present invention is particularly well suited for shallow isolation trench filling in the 0.13 micron geometry range, and smaller.
    Type: Grant
    Filed: March 27, 2000
    Date of Patent: April 9, 2002
    Assignee: Intel Corporation
    Inventors: Kelin J. Kuhn, Ian R. Post
  • Patent number: 4617669
    Abstract: In a slab laser, the optical pumping lamps extend transversely to the mean direction of the laser beam with the spatial period of the lamps being harmonically related to the spatial period of the zig-zag laser beam path within the slab, preferably with equal periods. In addition, the lamps are preferably positioned in registration over the lines of intersection of the central ray of the laser beam with respective broad face of the laser slab. A planar flashlamp reflector is employed for economy of fabrication. Directional lamp reflectors are employed for increasing laser efficiency and performance by discriminating against amplified surface waves.
    Type: Grant
    Filed: December 3, 1983
    Date of Patent: October 14, 1986
    Assignee: Board of Trustees, Leland Stanford, Jr. University
    Inventor: Kelin J. Kuhn
  • Patent number: 4563763
    Abstract: In a high average power slab laser, heat generated in the laser slab is conducted through a thin layer of thermally conductive gas, such as hydrogen, helium or air, and then through an optically transparent window into a flow of liquid coolant. In a preferred embodiment, a second flow of liquid coolant is employed for cooling of the pumping lamps such lamp liquid coolant flow being partitioned from the slab liquid coolant flow by means of an optically transparent partition through which the pump radiation is directed from the lamps to the slab. In another embodiment, the slab coolant flow is controlled so as to operate the laser slab in a self-annealing temperature regime, whereby thermal stresses are annealed out in use and higher average output beam power is obtained.
    Type: Grant
    Filed: August 22, 1983
    Date of Patent: January 7, 1986
    Assignee: Board of Trustees, Leland Stanford University
    Inventor: Kelin J. Kuhn