Abstract: A semiconductor structure with a stop layer for planarization process therein and a method for forming the same is disclosed. The method includes the steps of: forming a trench in a substrate and between active areas; filling the trench with isolation layer; doping the isolation layer with an element to form a doped isolation region; annealing the doped isolation region; and planarizing the annealed and doped isolation region and measuring a planarization depth thereof. The coefficients of thermal expansion (CTEs) of the stop layer, the dielectric layer, and the active area are different.

Abstract: A semiconductor manufacturing apparatus includes an air distributor inside a chamber. The air distributor includes a first annular plate and a second annular plate disposed in an interior volume of the chamber, and an inner surface of the first annular plate and an inner surface of the second annular plate are connected to each other. A hollow region is defined by the first annular plate and the second annular plate. A gas through hole is extended from an outer surface of the first annular plate to the inner surface of the first annular plate. A plurality of ditches are between the inner surface of the first annular plate and the inner surface of the second annular plate, wherein the ditches are connected with the gas through hole and extended from the gas through hole to the hollow region to blow gas toward the hollow region.

Abstract: A method includes forming a first fin protruding above a substrate, the first fin having a PMOS region; forming a first gate structure over the first fin in the PMOS region; forming a first spacer layer over the first fin and the first gate structure; and forming a second spacer layer over the first spacer layer. The method further includes performing a first etching process to remove the second spacer layer from a top surface and sidewalls of the first fin in the PMOS region; performing a second etching process to remove the first spacer layer from the top surface and the sidewalls of the first fin in the PMOS region; and epitaxially growing a first source/drain material over the first fin in the PMOS region, the first source/drain material extending along the top surface and the sidewalls of the first fin in the PMOS region.

Abstract: A target object selection method, a server, and a computer storage medium are disclosed. The method includes selecting a first one candidate user meeting a first condition in a target area, the first condition characterizing a user who has appeared in the target area; extracting a first social relationship chain of the at least one candidate user in the target area, the social relationship chain comprising a first related user who has a social relationship with the candidate user; and selecting a first one target user in the target area based on the first social relationship chain and sending information to the first target user.

Abstract: A method includes forming a first fin protruding above a substrate, the first fin having a PMOS region; forming a first gate structure over the first fin in the PMOS region; forming a first spacer layer over the first fin and the first gate structure; and forming a second spacer layer over the first spacer layer. The method further includes performing a first etching process to remove the second spacer layer from a top surface and sidewalls of the first fin in the PMOS region; performing a second etching process to remove the first spacer layer from the top surface and the sidewalls of the first fin in the PMOS region; and epitaxially growing a first source/drain material over the first fin in the PMOS region, the first source/drain material extending along the top surface and the sidewalls of the first fin in the PMOS region.

Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.

Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.

Abstract: Field effect transistor and methods of forming the same are disclosed. The field effect transistor includes a gate electrode, a contact etch stop layer (CESL), an inter layer dielectric (ILD) and a protection layer. The CESL includes SiCON and is disposed on a sidewall of the gate electrode. The IDL is laterally adjacent to the gate electrode. The protection layer covers the CESL and is disposed between the CESL and the ILD.

Abstract: A semiconductor manufacturing apparatus includes a chamber, a view port window on a sidewall of the chamber and configured to receive an optical emission spectroscopy (OES); and an air distributor located between the view port window and an inner space of the chamber. The air distributor includes a hollow region aligned with the transparent window and configured to generate an air curtain in the hollow region to isolate the view port from the inner space.

Abstract: A semiconductor structure with a stop layer for planarization process therein and a method for forming the same is disclosed. The method includes the steps of: forming a trench in a substrate and between active areas; filling the trench with isolation layer; doping the isolation layer with an element to form a doped isolation region; annealing the doped isolation region; and planarizing the annealed and doped isolation region and measuring a planarization depth thereof. The coefficients of thermal expansion (CTEs) of the stop layer, the dielectric layer, and the active area are different.

Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.

Abstract: In accordance with some embodiments, a method is provided. The method includes: forming a semiconductor fin protruding from a substrate; depositing a spacer layer over the semiconductor fin; after the depositing the spacer layer over the semiconductor fin, implanting a first dopant in the spacer layer and depositing a dopant layer of the first dopant on the spacer layer in alternating repeating steps; removing the dopant layer; and performing a thermal anneal process to drive the first dopant into the semiconductor fin from the spacer layer.

Abstract: A fin field-effect transistor (FinFET) structure and a method for forming the same are provided. The FinFET structure includes a first fin structure that protrudes from a first region of a substrate. A second fin structure protrudes from a second region of the substrate. Isolation regions cover lower portions of the first fin structure and the second fin structure and leave upper portions of the first fin structure and the second fin structure above the isolation regions. A first liner layer is positioned between the lower portion of the first fin structure and the isolation regions in the first region. A second liner layer covers the lower portion of the second fin structure and is positioned between the second fin structure and the isolation regions in the second region. The first liner layer and the second liner layer are formed of different materials.

Abstract: A method includes forming a semiconductor capping layer over a first fin in a first region of a substrate, forming a dielectric layer over the semiconductor capping layer, and forming an insulation material over the dielectric layer, an upper surface of the insulation material extending further away from the substrate than an upper surface of the first fin. The method further includes recessing the insulation material to expose a top portion of the first fin, and forming a gate structure over the top portion of the first fin.

Abstract: A method for fabricating a shallow trench isolation (STI) structure comprises the following steps. A silane-base precursor having a volumetric flowrate of 500 to 750 sccm and a nitrogen-base precursor having a volumetric flowrate of 300 to 600 sccm are introduced and mixed under a first pressure ranging from 0.5 to 1.5 torr at a first temperature ranging from 30 to 105 centigrade to deposit a flowable dielectric layer in a trench of a substrate. Then, ozone gas and oxygen gas are introduced and mixed under a second pressure ranging from 300 to 650 torr at a second temperature ranging from 50 to 250 centigrade to treat the flowable dielectric layer, wherein a volumetric flowrate ratio of ozone gas and oxygen gas ranges from 1:1 to 3:1. A method for fabricating a FinFET is provided.

Abstract: A method includes forming a flowable dielectric layer in a trench of a substrate; curing the flowable dielectric layer; and annealing the cured flowable dielectric layer to form an insulation structure and a liner layer. The insulation structure is formed in the trench, the liner layer is formed between the insulation structure and the substrate, and the liner layer includes nitrogen.

Abstract: One or more techniques or systems for forming a contact structure for a deep trench capacitor (DTC) are provided herein. In some embodiments, a contact structure includes a substrate region, a first region, a second region, contact landings, a first trench region, a first landing region, and a second trench region. In some embodiments, a first region is over the substrate region and a second region is over the first region. For example, the first region and the second region are in the first trench region or the second trench region. Additionally, a contact landing over the first trench region, the second trench region, or the first landing region is in contact with the first region, the second region, or the substrate region. In this manner, additional contacts are provided and landing area is reduced, thus reducing resistance of the DTC, for example.

Abstract: A semiconductor structure with a stop layer for planarization process therein and a method for forming the same is disclosed. The method includes the steps of: forming a trench in a substrate and between active areas; filling the trench with isolation layer; doping the isolation layer with an element to form a doped isolation region; annealing the doped isolation region; and planarizing the annealed and doped isolation region and measuring a planarization depth thereof. The coefficients of thermal expansion (CTEs) of the stop layer, the dielectric layer, and the active area are different.

Abstract: A trench structure of a semiconductor device includes a substrate, an isolation structure, and a liner layer. The substrate has a trench therein. The isolation structure is disposed in the trench. The liner layer is disposed between the substrate and the isolation structure. The liner layer includes nitrogen, and the liner layer has spatially various nitrogen concentration.

Abstract: A semiconductor structure with a stop layer for planarization process therein and a method for forming the same is disclosed. The method includes the steps of: forming a trench in a substrate and between active areas; filling the trench with isolation layer; doping the isolation layer with an element to form a doped isolation region; annealing the doped isolation region; and planarizing the annealed and doped isolation region and measuring a planarization depth thereof. The coefficients of thermal expansion (CTEs) of the stop layer, the dielectric layer, and the active area are different.