Abstract: A method for fabricating a shallow trench isolation (STI) structure comprises the following steps. A silane-base precursor having a volumetric flowrate of 500 to 750 sccm and a nitrogen-base precursor having a volumetric flowrate of 300 to 600 sccm are introduced and mixed under a first pressure ranging from 0.5 to 1.5 torr at a first temperature ranging from 30 to 105 centigrade to deposit a flowable dielectric layer in a trench of a substrate. Then, ozone gas and oxygen gas are introduced and mixed under a second pressure ranging from 300 to 650 torr at a second temperature ranging from 50 to 250 centigrade to treat the flowable dielectric layer, wherein a volumetric flowrate ratio of ozone gas and oxygen gas ranges from 1:1 to 3:1. A method for fabricating a FinFET is provided.

Abstract: A system and method that manages listings is provided. In example embodiments, a first listing for offering an item is created. A second listing that is an adjustment to the first listing that includes a different attribute is then created. A result of the first listing and a result of the second listing are evaluated. An optimal listing based on the result of the first listing and the result of the second listing is determined.

Abstract: A fin field effect transistor (FinFET) including a substrate, a plurality of insulators, and a gate stack is provided. The substrate includes a plurality of trenches and at least one semiconductor fin between the trenches. The insulators are disposed in the trenches and include doped regions distributed therein. The gate stack partially covers the at least one semiconductor fin and the insulators. A method for fabricating the aforesaid FinFET is also discussed.

Abstract: A phase change memory (PCM) cell with a heating element electrically isolated from laterally surrounding regions of the PCM cell by a cavity is provided. A dielectric region is arranged between first and second conductors. A heating plug is arranged within a hole extending through the dielectric region to the first conductor. The heating plug includes a heating element running along sidewalls of the hole, and includes a sidewall structure including a cavity arranged between the heating element and the sidewalls. A phase change element is in thermal communication with the heating plug and arranged between the heating plug and the second conductor. Also provide is a method for manufacturing the PCM cell.

Abstract: A semiconductor structure with a stop layer for planarization process therein and a method for forming the same is disclosed. The method includes the steps of: forming a trench in a substrate and between active areas; filling the trench with isolation layer; doping the isolation layer with an element to form a doped isolation region; annealing the doped isolation region; and planarizing the annealed and doped isolation region and measuring a planarization depth thereof. The coefficients of thermal expansion (CTEs) of the stop layer, the dielectric layer, and the active area are different.

Abstract: A method of manufacturing a capacitive device. The method includes doping a substrate to form a well region, forming M shoulder portions and (M?1) trenches in the substrate, depositing (M?1) sets of stacked layers along an upper surface of each shoulder portion of the M shoulder portions, sidewalls of the (M?1) trenches, and a bottom surface of each trench of the (M?1) trenches, and etching a plurality of contact holes variously exposing the well region or conductive layers of the (M?1) sets of stacked layers by N patterned masks. An m-th trench of the (M?1) trenches is between an m-th shoulder portion and an (m+1)-th shoulder portion of the M shoulder portions. M is a positive integer equal to or greater than 2 and m is a positive integer from 1 to (M?1). N is a positive integer less than M. Each contact hole of the plurality of contact holes is directly on or above a corresponding shoulder portion of the M shoulder portions.

Abstract: A trench structure of a semiconductor device includes a substrate, an isolation structure, and a liner layer. The substrate has a trench therein. The isolation structure is disposed in the trench. The liner layer is disposed between the substrate and the isolation structure. The liner layer includes nitrogen, and the liner layer has spatially various nitrogen concentration.

Abstract: A method of manufacturing a capacitive device. The method includes doping a substrate to form a well region, forming M shoulder portions and (M?1) trenches in the substrate, depositing (M?1) sets of stacked layers along an upper surface of each shoulder portion of the M shoulder portions, sidewalls of the (M?1) trenches, and a bottom surface of each trench of the (M?1) trenches, and etching a plurality of contact holes variously exposing the well region or conductive layers of the (M?1) sets of stacked layers by N patterned masks. An m-th trench of the (M?1) trenches is between an m-th shoulder portion and an (m+1)-th shoulder portion of the M shoulder portions. M is a positive integer equal to or greater than 2 and m is a positive integer from 1 to (M?1). N is a positive integer less than M. Each contact hole of the plurality of contact holes is directly on or above a corresponding shoulder portion of the M shoulder portions.

Abstract: A method for imaging episcleral vessels in an eye includes injecting the eye with a contrast agent, positioning an imaging probe proximate to a limbus of the eye, acquiring a plurality of images along a circumference of the limbus and applying a vessel segmentation algorithm to the plurality of images to quantify episcleral diameter and density in real-time. A system for imaging episcleral vessels in an eye includes a processing unit operably connected to an imaging probe and a visual feedback device. In certain embodiments, the contrast agent includes fluorescein. In certain embodiments, the episcleral diameter and density is displayed in an image on a visual feedback device. In certain embodiments, the method is part of a treatment for relieving intraocular pressure in an eye that can include the steps of identifying a target treatment area based on the image and applying a MIGS treatment in the target treatment area.

Abstract: A capacitive device includes a substrate, a well structure buried in the substrate, a first stacked layer that includes a first dielectric layer and a first conductive layer, a cap dielectric layer, and a first electrode. The well has a predetermined doping type. The well includes a first shoulder portion having an upper surface, a second shoulder portion having an upper surface, and a first trench between the first and second shoulder portions. The first trench has sidewalls and a bottom surface. The first dielectric layer is lined along at least a portion of the upper surfaces of the first and second shoulder portions, the sidewalls of the first trench, and the bottom surface of the first trench. The first conductive layer is lined along the first dielectric layer. The cap dielectric layer is over the well, the first dielectric layer, and the first conductive layer.

Abstract: A phase change memory (PCM) cell with a heating element electrically isolated from laterally surrounding regions of the PCM cell by a cavity is provided. A dielectric region is arranged between first and second conductors. A heating plug is arranged within a hole extending through the dielectric region to the first conductor. The heating plug includes a heating element running along sidewalls of the hole, and includes a sidewall structure including a cavity arranged between the heating element and the sidewalls. A phase change element is in thermal communication with the heating plug and arranged between the heating plug and the second conductor. Also provide is a method for manufacturing the PCM cell.

Abstract: An apparatus for processing a semiconductor wafer includes a factory interface configured to couple with a manufacturing chamber. The factory interface includes a robot; an orienter adjacent to the robot; and a particle remover above the orienter and facing toward a wafer. The particle remover is configured to blow ionized gas on a surface of the wafer so as to remove particles.

Abstract: A semiconductor manufacturing apparatus includes a chamber, a view port window on a sidewall of the chamber and configured to receive an optical emission spectroscopy (OES); and an air distributor located between the view port window and an inner space of the chamber. The air distributor includes a hollow region aligned with the transparent window and configured to generate an air curtain in the hollow region to isolate the view port from the inner space.

Abstract: A capacitive device includes a substrate, a well structure buried in the substrate, a first stacked layer that includes a first dielectric layer and a first conductive layer, a cap dielectric layer, and a first electrode. The well has a predetermined doping type. The well includes a first shoulder portion having an upper surface, a second shoulder portion having an upper surface, and a first trench between the first and second shoulder portions. The first trench has sidewalls and a bottom surface. The first dielectric layer is lined along at least a portion of the upper surfaces of the first and second shoulder portions, the sidewalls of the first trench, and the bottom surface of the first trench. The first conductive layer is lined along the first dielectric layer. The cap dielectric layer is over the well, the first dielectric layer, and the first conductive layer.

Abstract: A novel method for manufacturing a semiconductor device and a semiconductor device are provided. The semiconductor device includes a substrate, a trench capacitor, a contact pad, an inter-layer dielectric (ILD) layer and contact elements. The trench capacitor includes a doped region, a first dielectric layer, a bottom electrode, a second dielectric layer and a top electrode, in which the contact pad is positioned on the doped region. The ILD layer has contact windows, and the contact elements are disposed therein. Because of the presence of the contact pad positioned on the doped region, the thickness of the ILD layer over the top electrode is increased but still satisfying the requirement of the maximum depth limit to the contact windows of etching the ILD layer.

Abstract: A capacitive device includes a well, a first dielectric layer, a first conductive layer, a cap dielectric layer, and a first electrode. The well includes a first shoulder portion having an upper surface, a second shoulder portion having an upper surface, and a first trench, sandwiched between the first and second shoulder portions, having sidewalls and a bottom surfaces. The first dielectric layer is lined along at least a portion of the upper surfaces of the first and second shoulder portions, the sidewalls of the first trench, and the bottom surface of the first trench. The first conductive layer is lined along the first dielectric layer. The cap dielectric layer is over the well, the first dielectric layer, and the first conductive layer. The first electrode is in contact with the first shoulder portion.

Abstract: A capacitive device includes a well, a first dielectric layer, a first conductive layer, a cap dielectric layer, and a first electrode. The well includes a first shoulder portion having an upper surface, a second shoulder portion having an upper surface, and a first trench, sandwiched between the first and second shoulder portions, having sidewalls and a bottom surfaces. The first dielectric layer is lined along at least a portion of the upper surfaces of the first and second shoulder portions, the sidewalls of the first trench, and the bottom surface of the first trench. The first conductive layer is lined along the first dielectric layer. The cap dielectric layer is over the well, the first dielectric layer, and the first conductive layer. The first electrode is in contact with the first shoulder portion.

Abstract: In a method for displaying a notification, a display device receives a push notification associated with an application program through a communication network, and a visual media signal from an external computing device. The display device subsequently generates a to-be-displayed message based on the push notification, and a visual media based on the visual media signal. Then, the display device displays at least one of the visual media and the to-be-displayed message on a display screen of the display device. In cases that the display device is connected to the external computing device, the display device displays the visual media and the to-be-displayed message simultaneously on the display screen.

Abstract: A novel method for manufacturing a semiconductor device and a semiconductor device are provided. The semiconductor device includes a substrate, a trench capacitor, a contact pad, an inter-layer dielectric (ILD) layer and contact elements. The trench capacitor includes a doped region, a first dielectric layer, a bottom electrode, a second dielectric layer and a top electrode, in which the contact pad is positioned on the doped region. The ILD layer has contact windows, and the contact elements are disposed therein. Because of the presence of the contact pad positioned on the doped region, the thickness of the ILD layer over the top electrode is increased but still satisfying the requirement of the maximum depth limit to the contact windows of etching the ILD layer.

Abstract: A protecting structure of an uninterruptible power supply prevents the uninterruptible power supply. The uninterruptible power supply device has a switch with a switching piece. The protecting structure includes a chassis, a sensor and a cover body. The chassis has an opening slot, the uninterruptible power supply device is installed in the chassis, and the switching piece is disposed corresponding to the opening slot. The sensor is provided on a side of the opening slot of the chassis and electrically connected with the uninterruptible power supply device. The cover body includes a cover plate and at least one blocking member connecting with the cover plate. The cover plate covers the opening slot, wherein the switching piece ejects the blocking member to expose the opening slot when the covered switching piece is switched from a first position to a second position.