Abstract: A described example includes: a heat slug having a board side surface and an opposite top side surface; a package substrate mounted to the heat slug, the package substrate including overhanging leads extending over the board side surface of the heat slug, the package substrate having downset portions including a downset rail that runs along one side of a die mount area; at least one semiconductor device having a backside surface mounted to the board side surface of the heat slug; electrical connections coupling bond pads of the semiconductor device to the overhanging leads of the package substrate and to the downset rail; and mold compound covering the at least one semiconductor device, the electrical connections, a portion of the leads and the board side surface of the heat slug, the top side surface at least partially exposed from the mold compound.

Abstract: This description relates generally to semiconductor devices and processes. A method for forming a packaged semiconductor package can include attaching a front side of a metal layer to a die pad of a leadframe that includes conductive terminals, so a periphery portion of the metal layer extends beyond a periphery pad surface of the die pad, and a portion of a half-etched cavity on the front side of the metal layer is located near the periphery pad surface of the die pad. The method further includes attaching a semiconductor device to the die pad and encapsulating the semiconductor device, the front side of the metal layer, a portion of a back side of the metal layer, and a portion of the conductive terminals to form a packaged semiconductor device.

Abstract: A microelectronic device includes a magnetic component having a first magnetic core segment and a second magnetic core segment, with a winding lamina between them. The first magnetic core segment includes a winding support portion with ferromagnetic material. The winding lamina is attached to the winding support portion. The first magnetic core segment also includes an extension portion with ferromagnetic material extending from the winding support portion. The winding lamina has winding loops of electrically conductive material that surround ferromagnetic material. A filler material is formed between the winding lamina and the first magnetic core segment, contacting both the winding lamina and the first magnetic core segment. The second magnetic core segment is attached to the extension portion of the first magnetic core segment. The second magnetic core segment includes ferromagnetic material. The winding loops are electrically coupled to external leads through electrical connections.

Abstract: A semiconductor device that has at least one semiconductor chip attached to a leadframe made of sheet metal of unencumbered full thickness. The leadframe has leads of a first subset that alternate with leads of a second subset. The leads of the first and second subsets have elongated straight lead portions that are parallel to each other in a planar array. A cover layer of insulating material is located over portions of un-encapsulated lead surfaces. The portions of the leads of the first and second subsets that don't have the cover layer have a metallurgical configuration that creates an affinity for solder wetting.

Abstract: A stacked die semiconductor package includes a leadframe including a die pad and lead terminals on at least two sides of the die pad, a top die having circuitry coupled to bond pads, and bottom die having a back side that is attached by die attach material to the die pad and a top side having at least one redistribution layer (RDL) over and coupled to a top metal level including connections to input/output (IO) nodes on the top metal level. The RDL provides a metal pattern including wirebond pads that match locations of the bond pads of the top die. The bond pads on the top die are flip-chip attached to the wirebond pads of the bottom die, and the bond wires are positioned between the wirebond pads and the lead terminals.

Abstract: A stacked die semiconductor package includes a leadframe including a die pad and lead terminals on at least two sides of the die pad, a top die having circuitry coupled to bond pads, and bottom die having a back side that is attached by die attach material to the die pad and a top side having at least one redistribution layer (RDL) over and coupled to a top metal level including connections to input/output (IO) nodes on the top metal level. The RDL provides a metal pattern including wirebond pads that match locations of the bond pads of the top die. The bond pads on the top die are flip-chip attached to the wirebond pads of the bottom die, and the bond wires are positioned between the wirebond pads and the lead terminals.

Abstract: In a described example, an apparatus includes a substrate with a first surface and an opposing second surface. The substrate includes a trench extending into the substrate from the first surface, a die mounting area adjacent to the trench, a first plurality of leads, and a second plurality of leads. The second plurality of leads are spaced from the trench to electrically isolate the second plurality of leads. The apparatus further includes a first mold compound in the trench forming a filled trench and in the space between the trench and the second plurality of leads. A first die is attached to the first surface of the substrate and a second die is attached to a surface of the first mold compound in the filled trench.

Abstract: A semiconductor device that has at least one semiconductor chip attached to a leadframe made of sheet metal of unencumbered full thickness. The leadframe has leads of a first subset that alternate with leads of a second subset. The leads of the first and second subsets have elongated straight lead portions that are parallel to each other in a planar array. A cover layer of insulating material is located over portions of un-encapsulated lead surfaces. The portions of the leads of the first and second subsets that don't have the cover layer have a metallurgical configuration that creates an affinity for solder wetting.

Abstract: A dual leadframe (100) for semiconductor systems comprising a first leadframe (110) having first metal zones separated by first gaps, the first zones including portions of reduced thickness and joint provisions in selected first locations, and further a second leadframe (120) having second metal zones separated by second gaps, the second zones including portions of reduced thickness and joint provisions (150) in selected second locations matching the first locations. The second leadframe is stacked on top of the first leadframe and the joint provisions of the matching second and first locations linked together. The resulting dual leadframe may further include insulating material (140) filling the first and second gaps and the zone portions of reduced thickness, and has insulating surfaces coplanar with the top and bottom metallic surfaces.

Abstract: A semiconductor device that has at least one semiconductor chip attached to a leadframe made of sheet metal of unencumbered full thickness. The leadframe has leads of a first subset that alternate with leads of a second subset. The leads of the first and second subsets have elongated straight lead portions that are parallel to each other in a planar array. A cover layer of insulating material is located over portions of un-encapsulated lead surfaces. The portions of the leads of the first and second subsets that don't have the cover layer have a metallurgical configuration that creates an affinity for solder wetting.

Abstract: An application-centric continuous delivery (ACCID) architecture provides a service that automates the configuration and management of end-to-end application lifecycle management (ALM) tools, through an innovative application-centric metadata model that can be customized through a self-service portal. With the ACCID architecture, IT organizations can provide version management, build automation, test automation, artifact management, infrastructure build, and automated application deployment that is consistent with global IT policy and governance and delivered as a service to organizations. The ACCID architecture references customized application metadata models that describe the application services, ALM requirements, and target infrastructure, to employ end-to-end automation of: the software deployment lifecycle and promotion across application environments, e.g., Development, Test, Pre-Production, and Production environments, using private, public, or hybrid cloud deployment models.

Abstract: A dual leadframe (100) for semiconductor systems comprising a first leadframe (110) having first metal zones separated by first gaps, the first zones including portions of reduced thickness and joint provisions in selected first locations, and further a second leadframe (120) having second metal zones separated by second gaps, the second zones including portions of reduced thickness and joint provisions (150) in selected second locations matching the first locations. The second leadframe is stacked on top of the first leadframe and the joint provisions of the matching second and first locations linked together. The resulting dual leadframe may further include insulating material (140) filling the first and second gaps and the zone portions of reduced thickness, and has insulating surfaces coplanar with the top and bottom metallic surfaces.

Abstract: A dual leadframe (100) for semiconductor systems comprising a first leadframe (110) having first metal zones separated by first gaps, the first zones including portions of reduced thickness and joint provisions in selected first locations, and further a second leadframe (120) having second metal zones separated by second gaps, the second zones including portions of reduced thickness and joint provisions (150) in selected second locations matching the first locations. The second leadframe is stacked on top of the first leadframe and the joint provisions of the matching second and first locations linked together. The resulting dual leadframe may further include insulating material (140) filling the first and second gaps and the zone portions of reduced thickness, and has insulating surfaces coplanar with the top and bottom metallic surfaces.

Abstract: A semiconductor device that has at least one semiconductor chip attached to a leadframe made of sheet metal of unencumbered full thickness. The leadframe has leads of a first subset that alternate with leads of a second subset. The leads of the first and second subsets have elongated straight lead portions that are parallel to each other in a planar array. A cover layer of insulating material is located over portions of un-encapsulated lead surfaces. The portions of the leads of the first and second subsets that don't have the cover layer have a metallurgical configuration that creates an affinity for solder wetting.

Abstract: An application-centric continuous delivery (ACCID) architecture provides a service that automates the configuration and management of end-to-end application lifecycle management (ALM) tools, through an innovative application-centric metadata model that can be customized through a self-service portal. With the ACCID architecture, IT organizations can provide version management, build automation, test automation, artifact management, infrastructure build, and automated application deployment that is consistent with global IT policy and governance and delivered as a service to organizations. The ACCID architecture references customized application metadata models that describe the application services, ALM requirements, and target infrastructure, to employ end-to-end automation of: the software deployment lifecycle and promotion across application environments, e.g., Development, Test, Pre-Production, and Production environments, using private, public, or hybrid cloud deployment models.

Abstract: A dual leadframe (100) for semiconductor systems comprising a first leadframe (110) having first metal zones separated by first gaps, the first zones including portions of reduced thickness and joint provisions in selected first locations, and further a second leadframe (120) having second metal zones separated by second gaps, the second zones including portions of reduced thickness and joint provisions (150) in selected second locations matching the first locations. The second leadframe is stacked on top of the first leadframe and the joint provisions of the matching second and first locations linked together. The resulting dual leadframe may further include insulating material (140) filling the first and second gaps and the zone portions of reduced thickness, and has insulating surfaces coplanar with the top and bottom metallic surfaces.

Abstract: An integrated circuit package configured to incorporate a lead frame and methods for its making are is described. The package comprising an IC with aluminum bond pads in communication with circuitry of the die with lead frame with silver bond pads. The package having gold bumps bonded between the aluminum bond pad of the die and the silver bond pad of the lead frame. The package including an encapsulant envelope and including various materials and bond pad structures and constructed in a manner formed by thermosonically or thermocompressionally bonding the gold balls to the bond pads. Also, disclosed are methods of making the package.

Abstract: Methods and systems are described for enabling the efficient fabrication of wedge-bonding of integrated circuit systems and electronic systems.

Abstract: Methods and systems are described for enabling the efficient fabrication of wedge-bonding of integrated circuit systems and electronic systems.

Abstract: Methods and systems are described for enabling the efficient fabrication of wedge bonding of integrated circuit systems and electronic systems. In particular a reverse bonding approach can be employed.