Patents by Inventor Ken Pomaranski

Ken Pomaranski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060245264
    Abstract: A computer system provides for both lock-step and free-step processor modes, allowing for an effective tradeoff between performance and data integrity.
    Type: Application
    Filed: April 19, 2005
    Publication date: November 2, 2006
    Inventors: Andrew Barr, Ken Pomaranski
  • Publication number: 20060248314
    Abstract: Systems and methods for repairing a processor are provided. In one embodiment, a method for repairing a processor is provided that includes, for example, the steps of initializing and executing an operating system, determining that a cache element is faulty, and swapping in a spare cache element for said faulty cache element while the operating system is executing.
    Type: Application
    Filed: February 17, 2006
    Publication date: November 2, 2006
    Inventors: Jeff Barlow, Jeff Brauch, Howard Calkin, Raymond Gratias, Stephen Hack, Lacey Joyal, Guy Kuntz, Ken Pomaranski, Michael Sedmak
  • Publication number: 20060248313
    Abstract: In one embodiment, a CPU cache management system is provided. The CPU management system includes, for example, a CPU chip and cache management logic. The CPU chip include cache elements that are initially in use and spare cache elements that not initially in use. The cache management logic determines whether currently-used cache elements are faulty. If a cache element is determined to be faulty, the cache management logic schedules a reboot of the computer and swaps in a spare cache element for the faulty currently-used cache element during the reboot.
    Type: Application
    Filed: February 17, 2006
    Publication date: November 2, 2006
    Inventors: Jeff Barlow, Jeff Brauch, Howard Calkin, Raymond Gratias, Stephen Hack, Lacey Joyal, Guy Kuntz, Ken Pomaranski, Michael Sedmak
  • Publication number: 20060236034
    Abstract: A processor can write its state to an external state cache. Thus, in the event of a processor failure, the stored state can be read and assumed, either by the original processor or another processor. Thus, a process can be resumed from the stored state rather than reconstructed from initial conditions.
    Type: Application
    Filed: April 19, 2005
    Publication date: October 19, 2006
    Inventors: Ken Pomaranski, Andrew Barr, Dale Shidla
  • Publication number: 20060233204
    Abstract: A computer system has redundant I/O interface modules for managing communications between an incorporating computer system and an external system such as a network or multi-port disk array. A redundant I/O interface manager directs communications through one of the redundant I/O interface modules, and switches the communications through the other, e.g., when a failure of the first I/O interface module is detected or predicted. The redundant I/O interface module appears to the operating system of the incorporating system as the first I/O interface module would so the switching is effectively invisible to the operating system.
    Type: Application
    Filed: April 19, 2005
    Publication date: October 19, 2006
    Inventors: Ken Pomaranski, Andrew Barr, Dale Shidla
  • Publication number: 20060236035
    Abstract: In one embodiment, a cache element allocation method is provided. Each cache element on a CPU is assigned a quality rank based on the error rate of the cache element. If an allocated cache element is deemed to be faulty, the quality rank of the faulty allocated cache element is compared with the quality rank of the non-allocated cache elements. If a non-allocated cache element has a lower quality rank than the allocated cache element, the non-allocated cache element is swapped in for the allocated cache element.
    Type: Application
    Filed: February 17, 2006
    Publication date: October 19, 2006
    Inventors: Jeff Barlow, Jeff Brauch, Howard Calkin, Raymond Gratias, Stephen Hack, Lacey Joyal, Guy Kuntz, Ken Pomaranski, Michael Sedmak
  • Publication number: 20060230231
    Abstract: In one embodiment, a cache element allocation method is provided. Each cache element on a CPU is assigned a quality rank based on the error rate of the cache element. If an allocated cache element is deemed to be faulty, the quality rank of the faulty allocated cache element is compared with the quality rank of the non-allocated cache elements. If a non-allocated cache element has a lower quality rank than the allocated cache element, the non-allocated cache element is swapped in for the allocated cache element.
    Type: Application
    Filed: February 17, 2006
    Publication date: October 12, 2006
    Inventors: Jeff Barlow, Jeff Brauch, Howard Calkin, Raymond Gratias, Stephen Hack, Lacey Joyal, Guy Kuntz, Ken Pomaranski, Michael Sedmak
  • Publication number: 20060230254
    Abstract: Systems and methods for repairing a processor are provided. In one embodiment, a method for repairing a processor is provided that includes, for example, the steps of initializing and executing an operating system, determining that a cache element is faulty, and swapping in a spare cache element for said faulty cache element while the operating system is executing.
    Type: Application
    Filed: February 17, 2006
    Publication date: October 12, 2006
    Inventors: Jeff Barlow, Jeff Brauch, Howard Calkin, Raymond Gratias, Stephen Hack, Lacey Joyal, Guy Kuntz, Ken Pomaranski, Michael Sedmak
  • Publication number: 20060230308
    Abstract: Systems and methods for conducting processor health-checks are provided. In one embodiment, a method for evaluating the status of a processor is provided. The method includes, for example, initializing and executing an operating system, de-allocating the processor from the available pool or system resources and performing a health-check on the processor while the operating system is executing.
    Type: Application
    Filed: February 17, 2006
    Publication date: October 12, 2006
    Inventors: Jeff Barlow, Jeff Brauch, Howard Calkin, Raymond Gratias, Stephen Hack, Lacey Joyal, Guy Kuntz, Ken Pomaranski, Michael Sedmak
  • Publication number: 20060230255
    Abstract: Systems and methods for repairing a processor are provided. In one embodiment, a method for repairing a processor is provided that includes, for example, the steps of initializing and executing an operating system, determining that a cache element is faulty, and swapping in a spare cache element for said faulty cache element while the operating system is executing.
    Type: Application
    Filed: February 17, 2006
    Publication date: October 12, 2006
    Inventors: Jeff Barlow, Jeff Brauch, Howard Calkin, Raymond Gratias, Stephen Hack, Lacey Joyal, Guy Kuntz, Ken Pomaranski, Michael Sedmak
  • Publication number: 20060230230
    Abstract: In one embodiment, a cache element allocation method is provided. Each cache element on a CPU is assigned a quality rank based on the error rate of the cache element. If an allocated cache element is deemed to be faulty, the quality rank of the faulty allocated cache element is compared with the quality rank of the non-allocated cache elements. If a non-allocated cache element has a lower quality rank than the allocated cache element, the non-allocated cache element is swapped in for the allocated cache element.
    Type: Application
    Filed: February 17, 2006
    Publication date: October 12, 2006
    Inventors: Jeff Barlow, Jeff Brauch, Howard Calkin, Raymond Gratias, Stephen Hack, Lacey Joyal, Guy Kuntz, Ken Pomaranski, Michael Sedmak
  • Publication number: 20060230307
    Abstract: Systems and methods for conducting processor health-checks are provided. In one embodiment, a method for evaluating the status of a processor is provided. The method includes, for example, initializing and executing an operating system, de-allocating the processor from the available pool or system resources and performing a health-check on the processor while the operating system is executing.
    Type: Application
    Filed: February 17, 2006
    Publication date: October 12, 2006
    Inventors: Jeff Barlow, Jeff Brauch, Howard Calkin, Raymond Gratias, Stephen Hack, Lacey Joyal, Guy Kuntz, Ken Pomaranski, Michael Sedmark
  • Publication number: 20060053337
    Abstract: One embodiment disclosed relates to a method of preventative maintenance of a high-availability cluster. A least-recently-tested active node is determined. The least-recently-tested active node is swapped out from the HA cluster, and a stand-by node is swapped into the HA cluster. Other embodiments are also disclosed.
    Type: Application
    Filed: September 8, 2004
    Publication date: March 9, 2006
    Inventors: Ken Pomaranski, Andrew Barr
  • Publication number: 20060053336
    Abstract: One embodiment disclosed relates to a high-availability cluster apparatus having a plurality of computing nodes and a hardware interface configured to connect to each of said nodes. The internode connections are coupled to the hardware interface to communicate node status signals between said nodes. A node is removable from being connected to the hardware interface without interrupting a topological continuity of the internode connections. Other embodiments are also disclosed.
    Type: Application
    Filed: September 8, 2004
    Publication date: March 9, 2006
    Inventors: Ken Pomaranski, Andrew Barr, Kenneth Konesky
  • Publication number: 20060053330
    Abstract: One embodiment disclosed relates to a high-availability (HA) cluster system. The cluster includes a plurality of computing nodes and clustering software configured to manage the cluster. In addition, the cluster includes a smart card, including a microprocessor-based system, communicatively connected to each of the nodes. Another embodiment disclosed relates to an apparatus adapted for use with a corresponding node of a high-availability (HA) cluster. The apparatus includes a microprocessor, control software, at least one input channel to receive data from the corresponding node, at least one output channel to send commands to the corresponding node, at least one input link to receive commands from clustering software of the HA cluster, and at least one output link to send information to the clustering software. Other embodiments are also disclosed.
    Type: Application
    Filed: September 8, 2004
    Publication date: March 9, 2006
    Inventors: Ken Pomaranski, Andrew Barr
  • Publication number: 20050289440
    Abstract: In one embodiment of the invention, a computer readable medium, comprising executable instructions for controlling application of an error correction code (ECC) algorithm in a memory subsystem, comprises code for recording occurrences of data corruption in data retrieved from the memory subsystem, code for analyzing the occurrences of data corruption to detect a repeated bit pattern of data corruption across different addresses of the memory subsystem, and code for controlling application of the ECC algorithm to erase bits associated with a repeated bit pattern, detected by the code for analyzing, from data retrieved from the memory subsystem.
    Type: Application
    Filed: June 29, 2004
    Publication date: December 29, 2005
    Inventors: John Nerl, Ken Pomaranski, Gary Gostin, Andrew Walton, David Soper
  • Publication number: 20050289402
    Abstract: In one embodiment, a system comprises non-volatile memory storing a page deallocation table (PDT), a memory controller for storing and retrieving data from a memory subsystem, the memory controller using an error correction code (ECC) algorithm to correct data corruption in retrieved data, a processor for executing an error analysis algorithm, the error analysis algorithm recording instances of data corruption in the PDT, deallocating memory regions associated with multiple occurrences of data corruption at single bit locations, the error analysis algorithm causing the memory controller to apply an erasure mode of the ECC algorithm upon detection of a repeated pattern of data corruption across different addresses of the memory subsystem, and removing entries in the PDT that correspond to data corruption addressed by application of the erasure mode.
    Type: Application
    Filed: June 29, 2004
    Publication date: December 29, 2005
    Inventors: John Nerl, Ken Pomaranski, Gary Gostin, Andrew Walton, David Soper
  • Publication number: 20050289439
    Abstract: In one embodiment, a computer readable medium comprises code for recording occurrences of data corruption in data retrieved from a memory subsystem, code for determining whether bit locations within the memory subsystem are associated with multiple occurrences of data corruption, code for deallocating, in response to the code for determining, memory regions containing bit locations associated with multiple occurrences of data corruption, code for analyzing patterns of data corruption repeated across multiple addresses of the memory subsystem, and code for controlling application of an error correction code (ECC) algorithm by the memory subsystem to erase bits associated with a repeated bit pattern, detected by the code for analyzing, from data retrieved from the memory subsystem.
    Type: Application
    Filed: June 29, 2004
    Publication date: December 29, 2005
    Inventors: John Nerl, Ken Pomaranski, Gary Gostin, Andrew Walton, David Soper
  • Publication number: 20050235124
    Abstract: Methodology, systems and media associated with selectively allocating memory are described. One exemplary method embodiment comprises receiving a quality data that identifies the quality of one or more allocatable subsets of a memory and selectively allocating a subset of memory from the allocatable memory to an application based, at least in part, on memory quality as identified in the quality data.
    Type: Application
    Filed: April 20, 2004
    Publication date: October 20, 2005
    Inventors: Ken Pomaranski, Andy Barr, Dale Shidla
  • Publication number: 20050188283
    Abstract: One embodiment disclosed relates to a method of status generation for a node of a high-availability cluster. A heartbeat signal is sent from the node through a network to the cluster. In addition, a current status of the node is determined, and the status is sent out through a specialized interface to a next node. Another embodiment disclosed relates to a method of cluster-wide management performed per node. A heartbeat input received from the previous node is checked. Furthermore, an up/down status input received from the previous node and a degraded status input received from the previous node are also checked. Another embodiment disclosed relates to a system for of a high-availability cluster. The system includes a general inter-node communication network that is configured to carry signals including heartbeat signals from the nodes. In addition, a separate inter-node communication channel is included for communicating node status signals.
    Type: Application
    Filed: January 23, 2004
    Publication date: August 25, 2005
    Inventors: Ken Pomaranski, Andrew Barr