Patents by Inventor Ken Pomaranski

Ken Pomaranski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050188265
    Abstract: One embodiment disclosed relates to a node system of a high-availability cluster. The node system includes at least a first register and an output port. The first register stores multi-state status data of the node, and the output port sends signals representing this multi-state status data. The multi-state status data includes at least one degraded state. The node system may also include a second register and an input port. The input port receives signals representing the multi-state status data of another node. The second stores this multi-state status data from the other node. Another embodiment disclosed relates to a method of status reporting for a node of a cluster. A set of rules is applied to determine current multi-state status of the node. The states of the multi-state status including a good state, a bad state, and at least one degraded state.
    Type: Application
    Filed: January 23, 2004
    Publication date: August 25, 2005
    Inventors: Ken Pomaranski, Andrew Barr
  • Publication number: 20050177779
    Abstract: One embodiment disclosed relates to a method of communicating status from a node of a cluster of computer systems. A first status signal is received from a computational node, and a default status signal is generated. The first status signal and the default status signal are used to generate a second status signal. Another embodiment disclosed relates to a method of communicating node status within a cluster of computer systems. A first signal indicative of the status of a current node is generated. A second signal indicative of the status of a preceding node is received. The first signal is transmitted to a next node if the current node is present in the cluster, and the second signal is transmitted to the next node if the current node has been removed from the cluster.
    Type: Application
    Filed: January 23, 2004
    Publication date: August 11, 2005
    Inventors: Ken Pomaranski, Andrew Barr
  • Publication number: 20050125187
    Abstract: A computer system comprising an operating system, a first component that comprises a first test module, a second component that comprises a second test module, and an interconnect coupling the first component and the second component is provided. The first test module is configured to provide a first test pattern to the second test module on the interconnect in response to a first signal from the operating system.
    Type: Application
    Filed: December 4, 2003
    Publication date: June 9, 2005
    Inventors: Ken Pomaranski, Andrew Barr, Dale Shidla
  • Publication number: 20050120268
    Abstract: A computer system that includes a processor, a first bus coupled to the processor, a memory controller coupled to the first bus, a memory coupled to the memory controller, a first input/output (I/O) controller coupled to the first bus, and a test module coupled to the first I/O controller is provided. The test module is configured to cause tests to be performed on the memory using the first bus.
    Type: Application
    Filed: November 14, 2003
    Publication date: June 2, 2005
    Inventors: Andrew Barr, Ken Pomaranski, Dale Shidla
  • Publication number: 20050116733
    Abstract: A method and corresponding apparatus for detecting and rejecting high impedance failures in chip interconnects use monitoring circuitry on a chip to provide accurate and pro-active prediction of interconnect failures. The apparatus may include a resistance continuity monitoring circuit (RCMC), and a signal path connecting a representative set of pins to the RCMC. The RCMC measures the resistance of a connection of the representative set of pins with a circuit board during system operation and outputs a measured resistance data. The apparatus further includes additional analog-to-digital (A/D) hardware to perform an analog to digital conversion of the measured resistance data. Additional on-chip circuitry and/or microcode may be used to perform an algorithm on the digital resistance data to generate an interconnect status signal. For example, the method may output a failure signal when the measured resistance data exceeds a threshold resistance value.
    Type: Application
    Filed: January 13, 2005
    Publication date: June 2, 2005
    Inventors: Andrew Barr, Ken Pomaranski, Dale Shidla
  • Publication number: 20050107987
    Abstract: A computer system that includes a processor, a memory controller coupled to the processor, a memory coupled to the memory controller, a first input/output (I/O) controller coupled to the memory controller, a first expansion slot coupled to the first I/O controller, and a test module card coupled to the first expansion slot wherein the test module card is configured to cause tests to be performed on the memory using direct memory access (DMA) is provided.
    Type: Application
    Filed: November 14, 2003
    Publication date: May 19, 2005
    Inventors: Andrew Barr, Ken Pomaranski, Dale Shidla
  • Publication number: 20050102655
    Abstract: A computer system comprising a processor configured to cause an operating system to be booted, a test module, and a component coupled to the test module and configured to receive a clock input is provided. The test module is configured to cause the clock input to be provided to the component at a first frequency, and the test module is configured to cause a first test to be performed on the component subsequent to the clock input being provided to the component at the first frequency and the operating system being booted.
    Type: Application
    Filed: November 7, 2003
    Publication date: May 12, 2005
    Inventors: Ken Pomaranski, Andrew Barr, Dale Shidla
  • Publication number: 20050102565
    Abstract: One embodiment disclosed relates to a method of executing program code on a target microprocessor with multiple CPU cores thereon. One of the CPU cores is selected for testing, and inter-core context switching is performed. Parallel execution occurs of diagnostic code on the selected CPU core and the program code on remaining CPU cores. Another embodiment disclosed relates to a microprocessor having a plurality of CPU cores integrated on the microprocessor chip. Inter-core communications circuitry is coupled to each of the CPU cores and configured to perform context switching between the CPU cores.
    Type: Application
    Filed: October 22, 2003
    Publication date: May 12, 2005
    Inventors: Andrew Barr, Ken Pomaranski, Dale Shidla
  • Publication number: 20050096863
    Abstract: A computer system comprising a first processor that is configured to cause an operating system to be booted, a test module, a component coupled to the test module, and a power supply coupled to the test module and the component is provided. The test module is configured to provide a first signal to the power supply to cause a first voltage to be provided to the component, and the test module is configured to cause a first test to be performed on the component subsequent to the first voltage being provided to the component and the operating system being booted.
    Type: Application
    Filed: October 31, 2003
    Publication date: May 5, 2005
    Inventors: Ken Pomaranski, Andrew Barr, Dale Shidla
  • Publication number: 20050096875
    Abstract: A computer system comprising a system module, a test module, a first cell, and a second cell is provided. The system module is configured to cause the test module to test the first cell subsequent to the second cell being allocated to a first instance of an operating system.
    Type: Application
    Filed: October 31, 2003
    Publication date: May 5, 2005
    Inventors: Ken Pomaranski, Andrew Barr, Dale Shidla
  • Publication number: 20050081191
    Abstract: One embodiment disclosed relates to a method of compiling a program to be executed on a target microprocessor with multiple execution units of a same type. The method includes selecting one of the execution units for testing and scheduling the parallel execution of program code and diagnostics code. The diagnostic code is scheduled to be executed on the selected execution unit. The program code is scheduled to be executed on remaining execution units of the same type.
    Type: Application
    Filed: October 14, 2003
    Publication date: April 14, 2005
    Inventors: Ken Pomaranski, Andrew Barr, Dale Shidla
  • Publication number: 20050080594
    Abstract: One embodiment disclosed relates to a method of compiling a program to be executed on a target central processing unit (CPU). The method includes opportunistically scheduling diagnostic testing of CPU registers. The method may include use of a predetermined level of aggressiveness for the scheduling of the register diagnostic testing. The scheduled diagnostic testing may include writing known data to a register, reading data from the register, and comparing the known data with the data that was read. If the comparison indicates a difference, then a jump may occur to a fault handler routine.
    Type: Application
    Filed: October 14, 2003
    Publication date: April 14, 2005
    Inventors: Andrew Barr, Ken Pomaranski, Dale Shidla
  • Publication number: 20050071690
    Abstract: One embodiment disclosed relates to a method of providing dynamic power redundancy for a system. A number of power supply units, n, that are presently in an up state is tracked. In addition, a number of power supply units, N, that are presently needed to supply power to the system is dynamically determined. If a margin of safety corresponding to a difference between n and N reaches a minimum acceptable level, then action is taken to increase the margin of safety.
    Type: Application
    Filed: September 26, 2003
    Publication date: March 31, 2005
    Inventors: Ken Pomaranski, Andrew Barr
  • Publication number: 20050071691
    Abstract: One embodiment disclosed relates to a method of providing dynamic temperature-adjusted power redundancy for a system. Tracking is performed of the number of power supply units, n, that are presently in an up state. The temperature in which the power supply units are operating is measured, and a temperature-adjusted number of power supply units, N, which are presently needed to supply power to the system, is dynamically determined.
    Type: Application
    Filed: September 26, 2003
    Publication date: March 31, 2005
    Inventors: Ken Pomaranski, Andrew Barr
  • Publication number: 20050060603
    Abstract: An example memory scrubbing logic is provided. The logic may be operably connectable to a main memory and a processor. The memory access logic may include a memory for mirroring a main memory location and a logic for scrubbing the main memory location.
    Type: Application
    Filed: September 11, 2003
    Publication date: March 17, 2005
    Inventors: Ken Pomaranski, Andy Barr, Dale Shidla
  • Publication number: 20050060514
    Abstract: An example memory quality assuring system is provided. The system may include a memory mapping logic configured to facilitate accessing memory locations and redirecting memory accessing operations. The system may also include a memory quality assurance logic configured to logically replace a first memory location with a second memory location, to initiate testing logically isolated memory locations, and to selectively logically remove tested memory locations based on the testing. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the application. It is submitted with the understanding that it will not be employed to interpret or limit the scope or meaning of the claims 37 CFR 1.72(b).
    Type: Application
    Filed: September 16, 2003
    Publication date: March 17, 2005
    Inventors: Ken Pomaranski, Andy Barr, Dale Shidla
  • Publication number: 20050055608
    Abstract: One embodiment disclosed relates to a method of providing CPU functional testing. Operations are executed on multiple functional units of a same type in the CPU. The outputs of the multiple functional units are automatically compared. The results of the comparison are checked only for redundant operations. Another embodiment disclosed relates to a microprocessor with built-in functional testing capability. The microprocessor includes multiple functional units of a same type and registers that receive outputs from the multiple functional units. In addition, comparator circuitry is built-in that also receives the outputs from the multiple functional units and compares the outputs to provide functional testing.
    Type: Application
    Filed: September 10, 2003
    Publication date: March 10, 2005
    Inventors: Dale Shidla, Andrew Barr, Ken Pomaranski
  • Publication number: 20050055674
    Abstract: One embodiment disclosed relates to a method of compiling a program to be executed on a target microprocessor. A cycle is identified during which a functional unit would otherwise be idle. A diagnostic operation is opportunistically scheduled for execution on the functional unit during that cycle, and a comparison is scheduled to compare a result from executing the diagnostic operation with a corresponding predetermined result.
    Type: Application
    Filed: September 10, 2003
    Publication date: March 10, 2005
    Inventors: Dale Shidla, Andrew Barr, Ken Pomaranski
  • Publication number: 20050055683
    Abstract: One embodiment disclosed relates to a method of compiling a program to be executed on a target microprocessor with multiple functional units of a same type. The method includes opportunistically scheduling a redundant operation on one of the functional units that would otherwise be idle during a cycle.
    Type: Application
    Filed: September 10, 2003
    Publication date: March 10, 2005
    Inventors: Dale Shidla, Andrew Barr, Ken Pomaranski
  • Publication number: 20050050276
    Abstract: A computer system comprising a processor, a memory, and a memory controller coupled to the processor and the memory is provided. The memory controller comprises a first cache and a cache control. The cache control is configured to cause a portion of the memory to be copied into the first cache. The cache control is configured to cause first information to be provided from the first cache to the processor in response to receiving a read transaction from the processor that includes an address in the portion of memory during testing of the portion.
    Type: Application
    Filed: August 29, 2003
    Publication date: March 3, 2005
    Inventors: Dale Shidla, Andrew Barr, Ken Pomaranski