Patents by Inventor Ken Tokashiki

Ken Tokashiki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240120237
    Abstract: Methods of forming high aspect ratio openings. The method comprises removing a portion of a dielectric material at a temperature less than about 0° C. to form at least one opening in the dielectric material. The at least one opening comprises an aspect ratio of greater than about 30:1. A protective material is formed in the at least one opening and on sidewalls of the dielectric material at a temperature less than about 0° C. Methods of forming high aspect ratio features are also disclosed, as are semiconductor devices.
    Type: Application
    Filed: December 18, 2023
    Publication date: April 11, 2024
    Inventors: Ken Tokashiki, John A. Smythe, Gurtej S. Sandhu
  • Patent number: 11854869
    Abstract: Methods of forming high aspect ratio openings. The method comprises removing a portion of a dielectric material at a temperature less than about 0° C. to form at least one opening in the dielectric material. The at least one opening comprises an aspect ratio of greater than about 30:1. A protective material is formed in the at least one opening and on sidewalls of the dielectric material at a temperature less than about 0° C. Methods of forming high aspect ratio features are also disclosed, as are semiconductor devices.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: December 26, 2023
    Inventors: Ken Tokashiki, John A. Smythe, Gurtej S. Sandhu
  • Publication number: 20220344200
    Abstract: Methods of forming high aspect ratio openings. The method comprises removing a portion of a dielectric material at a temperature less than about 0° C. to form at least one opening in the dielectric material. The at least one opening comprises an aspect ratio of greater than about 30:1. A protective material is formed in the at least one opening and on sidewalls of the dielectric material at a temperature less than about 0° C. Methods of forming high aspect ratio features are also disclosed, as are semiconductor devices.
    Type: Application
    Filed: July 7, 2022
    Publication date: October 27, 2022
    Inventors: Ken Tokashiki, John A. Smythe, Gurtej S. Sandhu
  • Patent number: 11417565
    Abstract: Methods of forming high aspect ratio openings. The method comprises removing a portion of a dielectric material at a temperature less than about 0° C. to form at least one opening in the dielectric material. The at least one opening comprises an aspect ratio of greater than about 30:1. A protective material is formed in the at least one opening and on sidewalls of the dielectric material at a temperature less than about 0° C. Methods of forming high aspect ratio features are also disclosed, as are semiconductor devices.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: August 16, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Ken Tokashiki, John A. Smythe, Gurtej S. Sandhu
  • Publication number: 20210143055
    Abstract: Methods of forming high aspect ratio openings. The method comprises removing a portion of a dielectric material at a temperature less than about 0° C. to form at least one opening in the dielectric material. The at least one opening comprises an aspect ratio of greater than about 30:1. A protective material is formed in the at least one opening and on sidewalls of the dielectric material at a temperature less than about 0° C. Methods of forming high aspect ratio features are also disclosed, as are semiconductor devices.
    Type: Application
    Filed: January 22, 2021
    Publication date: May 13, 2021
    Inventors: Ken Tokashiki, John A. Smythe, Gurtej S. Sandhu
  • Patent number: 10903109
    Abstract: Methods of forming high aspect ratio openings. The method comprises removing a portion of a dielectric material at a temperature less than about 0° C. to form at least one opening in the dielectric material. The at least one opening comprises an aspect ratio of greater than about 30:1. A protective material is formed in the at least one opening and on sidewalls of the dielectric material at a temperature less than about 0° C. Methods of forming high aspect ratio features are also disclosed, as are semiconductor devices.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: January 26, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Ken Tokashiki, John A. Smythe, Gurtej S. Sandhu
  • Patent number: 10811267
    Abstract: Methods of processing a semiconductor device structure comprise cooling an electrostatic chuck (ESC) for the semiconductor device structure, which comprises tiers of alternating materials including at least one dielectric material, to a temperature of ?30° C. or less, forming an opening in the semiconductor device structure with a plasma of a gas comprising a hydrogen-based gas and a fluorine-based gas in which the hydrogen-based gas comprises between about 10 vol % and 90 vol %. Other methods of processing a semiconductor device structure comprise cooling an ESC for the semiconductor device structure to a temperature of ?30° C. or less, applying a low frequency radio frequency (RF) having a non-sinusoidal waveform to the ESC, and forming an opening in the semiconductor device structure with a generated plasma. A processing system includes an ESC, a coolant system, and a low frequency RF power source generating a non-sinusoidal waveform comprising a combination of multiple sinusoidal waveforms.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: October 20, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Ken Tokashiki
  • Patent number: 10766057
    Abstract: A method of cleaning a tool for forming a semiconductor device includes heating a wafer comprising a ceramic material to heat at least the ceramic material, positioning the heated wafer on an electrostatic chuck of a tool for forming a semiconductor device such that deposits located proximate the heated wafer are heated to vaporize at least some of the deposits, and removing the vaporized deposits from the tool. Related methods of forming semiconductor devices, related systems, and related cleaning wafers are disclosed.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: September 8, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Ken Tokashiki, Gurtej S. Sandhu
  • Patent number: 10636839
    Abstract: Methods of forming a magnetic memory cell are disclosed. The method comprises forming a magnetic cell core material over a substrate, wherein forming the magnetic cell core comprises forming a first magnetic region over the substrate, forming a tunnel barrier material over the first magnetic region, and forming a second magnetic region over the tunnel barrier material. A temperature of at least one of the substrate or a wafer stage underlying the substrate is maintained at a temperature below about 0° C. and the magnetic cell core material is exposed to at least a first beam comprising one of an ion beam or a neutral beam comprising ions or elements of at least one noble gas to remove portions of the magnetic cell core material. Related magnetic memory cells and methods of forming an array of memory cells are also disclosed.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: April 28, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Ken Tokashiki
  • Patent number: 10600842
    Abstract: Methods of forming a magnetic memory cell are disclosed. The method comprises forming a magnetic cell core material over a substrate, wherein forming the magnetic cell core comprises forming a first magnetic region over the substrate, forming a tunnel barrier material over the first magnetic region, and forming a second magnetic region over the tunnel barrier material. A temperature of at least one of the substrate or a wafer stage underlying the substrate is maintained at a temperature below about 0° C. and the magnetic cell core material is exposed to at least a first beam comprising one of an ion beam or a neutral beam comprising ions or elements of at least one noble gas to remove portions of the magnetic cell core material. Related magnetic memory cells and methods of forming an array of memory cells are also disclosed.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: March 24, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Ken Tokashiki
  • Publication number: 20190206723
    Abstract: Methods of forming high aspect ratio openings. The method comprises removing a portion of a dielectric material at a temperature less than about 0° C. to form at least one opening in the dielectric material. The at least one opening comprises an aspect ratio of greater than about 30:1. A protective material is formed in the at least one opening and on sidewalls of the dielectric material at a temperature less than about 0° C. Methods of forming high aspect ratio features are also disclosed, as are semiconductor devices.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Inventors: Ken Tokashiki, John A. Smythe, Gurtej S. Sandhu
  • Publication number: 20190201945
    Abstract: A method of cleaning a tool for forming a semiconductor device includes heating a wafer comprising a ceramic material to heat at least the ceramic material, positioning the heated wafer on an electrostatic chuck of a tool for forming a semiconductor device such that deposits located proximate the heated wafer are heated to vaporize at least some of the deposits, and removing the vaporized deposits from the tool. Related methods of forming semiconductor devices, related systems, and related cleaning wafers are disclosed.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 4, 2019
    Inventors: Ken Tokashiki, Gurtej S. Sandhu
  • Publication number: 20190198333
    Abstract: Methods of processing a semiconductor device structure comprise cooling an electrostatic chuck (ESC) for the semiconductor device structure, which comprises tiers of alternating materials including at least one dielectric material, to a temperature of ?30° C. or less, forming an opening in the semiconductor device structure with a plasma of a gas comprising a hydrogen-based gas and a fluorine-based gas in which the hydrogen-based gas comprises between about 10 vol % and 90 vol %. Other methods of processing a semiconductor device structure comprise cooling an ESC for the semiconductor device structure to a temperature of ?30° C. or less, applying a low frequency radio frequency (RF) having a non-sinusoidal waveform to the ESC, and forming an opening in the semiconductor device structure with a generated plasma. A processing system includes an ESC, a coolant system, and a low frequency RF power source generating a non-sinusoidal waveform comprising a combination of multiple sinusoidal waveforms.
    Type: Application
    Filed: December 21, 2017
    Publication date: June 27, 2019
    Inventor: Ken Tokashiki
  • Publication number: 20190189687
    Abstract: Methods of forming a magnetic memory cell are disclosed. The method comprises forming a magnetic cell core material over a substrate, wherein forming the magnetic cell core comprises forming a first magnetic region over the substrate, forming a tunnel barrier material over the first magnetic region, and forming a second magnetic region over the tunnel barrier material. A temperature of at least one of the substrate or a wafer stage underlying the substrate is maintained at a temperature below about 0° C. and the magnetic cell core material is exposed to at least a first beam comprising one of an ion beam or a neutral beam comprising ions or elements of at least one noble gas to remove portions of the magnetic cell core material. Related magnetic memory cells and methods of forming an array of memory cells are also disclosed.
    Type: Application
    Filed: February 11, 2019
    Publication date: June 20, 2019
    Inventor: Ken Tokashiki
  • Publication number: 20180358407
    Abstract: Methods of forming a magnetic memory cell are disclosed. The method comprises forming a magnetic cell core material over a substrate, wherein forming the magnetic cell core comprises forming a first magnetic region over the substrate, forming a tunnel barrier material over the first magnetic region, and forming a second magnetic region over the tunnel barrier material. A temperature of at least one of the substrate or a wafer stage underlying the substrate is maintained at a temperature below about 0° C. and the magnetic cell core material is exposed to at least a first beam comprising one of an ion beam or a neutral beam comprising ions or elements of at least one noble gas to remove portions of the magnetic cell core material. Related magnetic memory cells and methods of forming an array of memory cells are also disclosed.
    Type: Application
    Filed: August 22, 2018
    Publication date: December 13, 2018
    Inventor: Ken Tokashiki
  • Patent number: 10103196
    Abstract: Methods of forming a magnetic memory cell are disclosed. The method comprises forming a magnetic cell core material over a substrate, wherein forming the magnetic cell core comprises forming a first magnetic region over the substrate, forming a tunnel barrier material over the first magnetic region, and forming a second magnetic region over the tunnel barrier material. A temperature of at least one of the substrate or a wafer stage underlying the substrate is maintained at a temperature below about 0° C. and the magnetic cell core material is exposed to at least a first beam comprising one of an ion beam or a neutral beam comprising ions or elements of at least one noble gas to remove portions of the magnetic cell core material. Related magnetic memory cells and methods of forming an array of memory cells are also disclosed.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: October 16, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Ken Tokashiki
  • Patent number: 9978932
    Abstract: Provided are semiconductor devices and methods of fabricating the same. The semiconductor device may include lower wires, upper wires crossing the lower wires, select elements provided at intersections between the lower and upper wires, and memory elements provided between the select elements and the upper wires. Each of the memory elements may include a lower electrode having a top width greater than a bottom width, and a data storage layer including a plurality of magnetic layers stacked on a top surface of the lower electrode and having a rounded edge.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: May 22, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyungjoon Kwon, Sechung Oh, Vladimir Urazaev, Ken Tokashiki, Jongchul Park, Gwang-Hyun Baek, Jaehun Seo, Sangmin Lee
  • Publication number: 20180061886
    Abstract: Methods of forming a magnetic memory cell are disclosed. The method comprises forming a magnetic cell core material over a substrate, wherein forming the magnetic cell core comprises forming a first magnetic region over the substrate, forming a tunnel barrier material over the first magnetic region, and forming a second magnetic region over the tunnel barrier material. A temperature of at least one of the substrate or a wafer stage underlying the substrate is maintained at a temperature below about 0° C. and the magnetic cell core material is exposed to at least a first beam comprising one of an ion beam or a neutral beam comprising ions or elements of at least one noble gas to remove portions of the magnetic cell core material. Related magnetic memory cells and methods of forming an array of memory cells are also disclosed.
    Type: Application
    Filed: August 30, 2016
    Publication date: March 1, 2018
    Inventor: Ken Tokashiki
  • Patent number: 9577183
    Abstract: In a method of manufacturing a MRAM device, a lower electrode is formed on a substrate. A first magnetic layer, a tunnel barrier layer, and a second magnetic layer are sequentially formed on the lower electrode layer. An etching mask is formed on the second magnetic layer. An ion beam etching process in which a first ion beam and a second ion beam are simultaneously emitted onto the substrate is performed to form a MTJ structure including a first magnetic layer pattern, a tunnel layer pattern, and a second magnetic layer pattern from the first magnetic layer, the tunnel barrier layer, and the second magnetic layer, respectively, the MTJ structure has no by-products remaining after the ion beam etching process is performed.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: February 21, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyoung-Sun Kim, Woo-Jin Kim, Ken Tokashiki
  • Publication number: 20160351795
    Abstract: Magnetic memory devices and methods of manufacturing the same are disclosed. A method may include forming a magnetic tunnel junction layer on a substrate, forming mask patterns on the magnetic tunnel junction layer, and sequentially performing a plurality of ion implantation processes using the mask patterns as ion implantation masks to form an isolation region in the magnetic tunnel junction layer. The isolation region may thereby define magnetic tunnel junction parts that are disposed under corresponding ones of the mask patterns. A magnetic memory device may include a plurality of magnetic tunnel junction parts electrically and magnetically isolated from each other through the isolation region.
    Type: Application
    Filed: August 10, 2016
    Publication date: December 1, 2016
    Inventors: Yoonchul CHO, Ken TOKASHIKI