Patents by Inventor Ken Yu
Ken Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955329Abstract: A method of forming a semiconductor device includes forming a first conductive feature on a bottom surface of an opening through a dielectric layer. The forming the first conductive feature leaves seeds on sidewalls of the opening. A treatment process is performed on the seeds to form treated seeds. The treated seeds are removed with a cleaning process. The cleaning process may include a rinse with deionized water. A second conductive feature is formed to fill the opening.Type: GrantFiled: April 28, 2023Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Wei Chang, Min-Hsiu Hung, Chun-I Tsai, Ken-Yu Chang, Yi-Ying Liu
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Publication number: 20240096819Abstract: There is provided a semiconductor package in which warpage of an interposer is prevented to improve product reliability. The semiconductor package comprising a first substrate including a first insulating layer, and a first conductive pattern disposed in the first insulating layer, a semiconductor chip disposed on the first substrate, an interposer disposed on the semiconductor chip, wherein the interposer includes a second insulating layer, and a second conductive pattern disposed in the second insulating layer, a support member disposed on a bottom surface of the second insulating layer and is in contact with an upper surface of the semiconductor chip, wherein the support member includes a first lower pad and a bump disposed under the first lower pad and a first connection member disposed between the first substrate and the interposer so as to connect the first conductive pattern and the second conductive pattern to each other.Type: ApplicationFiled: September 1, 2023Publication date: March 21, 2024Applicant: Samsung Electronics Co., Ltd.Inventor: Bong Ken YU
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Publication number: 20230402366Abstract: A semiconductor device includes a substrate, a source/drain region disposed in the substrate, a silicide structure disposed on the source/drain region, a first dielectric layer disposed over the substrate, a conductive contact disposed in the first dielectric layer and over the silicide structure, a second dielectric layer disposed over the first dielectric layer, a via contact disposed in the second dielectric layer and connected to the conductive contact, and a first metal surrounding the via contact.Type: ApplicationFiled: June 9, 2022Publication date: December 14, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shuen-Shin LIANG, Chia-Hung CHU, Po-Chin CHANG, Hsu-Kai CHANG, Kuan-Kan HU, Ken-Yu CHANG, Hung-Yi HUANG, Harry CHIEN, Wei-Yip LOH, Chun-I TSAI, Hong-Mao LEE, Sung-Li WANG, Pinyen LIN, Chuan-Hui SHEN
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Publication number: 20230386913Abstract: A semiconductor device includes a substrate, two semiconductor fins protruding from the substrate, an epitaxial feature over the two semiconductor fins and connected to the two semiconductor fins, a silicide layer over the epitaxial feature, a barrier layer over the silicide layer, and a metal layer over the barrier layer. The barrier layer includes a metal nitride. Along a boundary between the barrier layer and the metal layer, an atomic ratio of oxygen to metal nitride is about 0.15 to about 1.0.Type: ApplicationFiled: July 28, 2023Publication date: November 30, 2023Inventors: Cheng-Wei Chang, Yu-Ming Huang, Ethan Tseng, Ken-Yu Chang, Yi-Ying Liu
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Publication number: 20230369109Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back. After etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. A conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.Type: ApplicationFiled: July 26, 2023Publication date: November 16, 2023Inventors: Yu Shih Wang, Chun-I Tsai, Shian Wei Mao, Ken-Yu Chang, Ming-Hsing Tsai, Wei-Jung Lin
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Patent number: 11817384Abstract: The present disclosure provides an interconnect structure and a method for forming an interconnect structure. The method for forming an interconnect structure includes forming a bottom metal line in a first interlayer dielectric layer, forming a second interlayer dielectric layer over the bottom metal line, exposing a top surface of the bottom metal line, increasing a total surface area of the exposed top surface of the bottom metal line, forming a conductive via over the bottom metal line, and forming a top metal line over the conductive via.Type: GrantFiled: January 3, 2022Date of Patent: November 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Shuen-Shin Liang, Ken-Yu Chang, Hung-Yi Huang, Chien Chang, Chi-Hung Chuang, Kai-Yi Chu, Chun-I Tsai, Chun-Hsien Huang, Chih-Wei Chang, Hsu-Kai Chang, Chia-Hung Chu, Keng-Chu Lin, Sung-Li Wang
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Patent number: 11798843Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back. After etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. A conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.Type: GrantFiled: April 5, 2021Date of Patent: October 24, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu Shih Wang, Chun-I Tsai, Shian Wei Mao, Ken-Yu Chang, Ming-Hsing Tsai, Wei-Jung Lin
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Publication number: 20230314805Abstract: The present disclosure relates to an optic system for head wearable devices. The optic system comprises a first light emitter for emitting a plurality of first light signals, the first light emitter varies a direction of projection between a first spatial dimension limit and a second spatial dimension limit in a first dimension; a first light redirector; and a second light redirector. A geometry of the first light redirector is configured such that a light signal emitted by the first light emitter in proximity to the first spatial dimension limit has a total optical path length from the first light emitter to the eye of the viewer substantially equal to a total optical path length of another light signal emitted by the first light emitter in proximity to the second spatial dimension limit from the first light emitter to the eye of the viewer.Type: ApplicationFiled: June 28, 2022Publication date: October 5, 2023Applicant: HES IP HOLDINGS, LLCInventors: KEN-YU CHENG, GUO-HSUAN CHEN, FENG-CHUN YEH
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Publication number: 20230299168Abstract: A semiconductor device includes a semiconductor substrate, an epitaxial structure, a silicide structure, a conductive structure, and a protection segment. The epitaxial structure is disposed in the semiconductor substrate. The silicide structure is disposed in the epitaxial structure. The conductive structure is disposed over the silicide structure and is electrically connected to the silicide structure. The protection segment is made of metal nitride, is disposed over the silicide structure, and is disposed between the silicide structure and the conductive structure.Type: ApplicationFiled: March 15, 2022Publication date: September 21, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuan-Kan HU, Shuen-Shin LIANG, Chia-Hung CHU, Po-Chin CHANG, Hsu-Kai CHANG, Ken-Yu CHANG, Wei-Yip LOH, Hung-Yi HUANG, Harry CHIEN, Sung-Li WANG, Pinyen LIN, Chuan-Hui SHEN, Tzu-Pei CHEN, Yuting CHENG
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Patent number: 11762417Abstract: An optical film includes a rough surface having multiple measuring points constituting multiple virtual measuring planes in a given unit measuring area. A normal to each virtual measuring plane has an angle with a normal to a reference plane. On the reference plane, the projection area of the virtual measuring planes having the angle larger than 20 degrees ranges from 31% to 60% of the projection area of the given unit measuring area. The projection area of the virtual measuring planes having the angle larger than 50 degrees is less than 7% of the projection area of the given unit measuring area. 25% of the measuring points has the height larger than a first height. 75% of the measuring points has the height larger than a second height. The first height and the second height have a difference not less than 0.6 ?m and not larger than 2.5 ?m.Type: GrantFiled: November 6, 2020Date of Patent: September 19, 2023Assignee: AU OPTRONICS CORPORATIONInventors: Shu-Cheng Kung, Ken-Yu Liu, Kuan-Yu Tung
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Patent number: 11742240Abstract: A semiconductor device includes a substrate, two semiconductor fins protruding from the substrate, an epitaxial feature over the two semiconductor fins and connected to the two semiconductor fins, a silicide layer over the epitaxial feature, a barrier layer over the silicide layer, and a metal layer over the barrier layer. The barrier layer includes a metal nitride. Along a boundary between the barrier layer and the metal layer, an atomic ratio of oxygen to metal nitride is about 0.15 to about 1.0.Type: GrantFiled: February 21, 2022Date of Patent: August 29, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Wei Chang, Yu-Ming Huang, Ethan Tseng, Ken-Yu Chang, Yi-Ying Liu
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Publication number: 20230268173Abstract: A method of forming a semiconductor device includes forming a first conductive feature on a bottom surface of an opening through a dielectric layer. The forming the first conductive feature leaves seeds on sidewalls of the opening. A treatment process is performed on the seeds to form treated seeds. The treated seeds are removed with a cleaning process. The cleaning process may include a rinse with deionized water. A second conductive feature is formed to fill the opening.Type: ApplicationFiled: April 28, 2023Publication date: August 24, 2023Inventors: Cheng-Wei Chang, Min-Hsiu Hung, Chun-I Tsai, Ken-Yu Chang, Yi-Ying Liu
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Publication number: 20230268228Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.Type: ApplicationFiled: April 28, 2023Publication date: August 24, 2023Inventors: Ken-Yu Chang, Chun-I Tsai, Ming-Hsing Tsai, Wei-Jung Lin
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Publication number: 20230230916Abstract: A method for manufacturing a semiconductor device includes: forming a lower metal contact in a trench of a first dielectric structure, the lower metal contact having a height less than a depth of the trench and being made of a first metal material; forming an upper metal contact to fill the trench and to be in contact with the lower metal contact, the upper metal contact being formed of a second metal material different from the first metal material and having a bottom surface with a dimension the same as a dimension of a top surface of the lower metal contact; forming a second dielectric structure on the first dielectric structure; and forming a via contact penetrating through the second dielectric structure to be electrically connected to the upper metal contact, the via contact being formed of a metal material the same as the second metal material.Type: ApplicationFiled: January 18, 2022Publication date: July 20, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shuen-Shin LIANG, Chia-Hung CHU, Po-Chin CHANG, Tzu-Pei CHEN, Ken-Yu CHANG, Hung-Yi HUANG, Harry CHIEN, Wei-Yip LOH, Chun-I TSAI, Hong-Mao LEE, Sung-Li WANG, Pinyen LIN
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Publication number: 20230221465Abstract: A display device includes a display module and an anti-glare film on the display module. The anti-glare film includes a first anti-glare layer and a second anti-glare layer. The first anti-glare layer has a plurality of microstructures at an upper surface of the first anti-glare layer. A root-mean-square slope of the microstructures is more than 0 and is 0.2 or less. The second anti-glare layer is between the first anti-glare layer and the display module, and an inner haze of the second anti-glare layer is from 20% to 90%.Type: ApplicationFiled: August 9, 2022Publication date: July 13, 2023Inventors: Shu-Cheng KUNG, Ya-Chen KAO, Ken-Yu LIU
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Patent number: 11676859Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.Type: GrantFiled: July 12, 2021Date of Patent: June 13, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ken-Yu Chang, Chun-I Tsai, Ming-Hsing Tsai, Wei-Jung Lin
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Patent number: 11670499Abstract: A method of forming a semiconductor device includes forming a first conductive feature on a bottom surface of an opening through a dielectric layer. The forming the first conductive feature leaves seeds on sidewalls of the opening. A treatment process is performed on the seeds to form treated seeds. The treated seeds are removed with a cleaning process. The cleaning process may include a rinse with deionized water. A second conductive feature is formed to fill the opening.Type: GrantFiled: March 18, 2021Date of Patent: June 6, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Wei Chang, Min-Hsiu Hung, Chun-I Tsai, Ken-Yu Chang, Yi-Ying Liu
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Publication number: 20230095976Abstract: The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.Type: ApplicationFiled: December 5, 2022Publication date: March 30, 2023Inventors: Shuen-Shin LIANG, Chun-I TSAI, Chih-Wei CHANG, Chun-Hsien HUANG, Hung-Yi HUANG, Keng-Chu LIN, Ken-Yu CHANG, Sung-Li WANG, Chia-Hung CHU, Hsu-Kai CHANG
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Publication number: 20230071211Abstract: An anti-glare substrate, an anti-reflection film, and a display device are disclosed. The anti-glare substrate includes a first surface and a second surface disposed on opposite sides. The first surface includes a plurality of protrusion structures. Each protrusion structure includes a plurality of inclined planes. There is an angle ? between the normal direction of each inclined plane and the normal direction of the second surface. The sum of the vertical projection area of the inclined planes with ? less than 2.5° on the second surface is A<2.5, wherein the vertical projection area of the inclined planes is AT, wherein A < 2.5 A T ? 100 ? % ? 3.58 % . The anti-reflection film is for use with an anti-glare substrate. For a first assembly formed by disposing the anti-reflection film on the anti-glare substrate, the reflectances to blue ray, to green ray, and to red ray are close. The display device includes the anti-glare substrate and a display panel.Type: ApplicationFiled: August 4, 2022Publication date: March 9, 2023Inventors: KUAN-YU TUNG, KEN-YU LIU, SHANG WEI HSIEH
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Patent number: 11594609Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes forming a liner-free conductive structure on a cobalt conductive structure disposed on a substrate, depositing a cobalt layer on the liner-free conductive structure and exposing the liner-free conductive structure to a heat treatment. The method further includes removing the cobalt layer from the liner-free conductive structure.Type: GrantFiled: May 29, 2020Date of Patent: February 28, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shuen-Shin Liang, Chun-I Tsai, Chih-Wei Chang, Chun-Hsien Huang, Hung-Yi Huang, Keng-Chu Lin, Ken-Yu Chang, Sung-Li Wang, Chia-Hung Chu, Hsu-Kai Chang