Patents by Inventor Ken Yu
Ken Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10121424Abstract: A display device includes a first substrate, a second substrate, a display medium, a first pixel electrode, a second pixel electrode and a transparent electrode. Sub-pixel units are defined on the first substrate and the second substrate. A sub-pixel unit has a first sub-pixel and a second sub-pixel. The transparent electrode is disposed on the second substrate, and the transparent electrode receives a first common potential and a second common potential. When grey levels displayed by the first sub-pixel and the second sub-pixel are in the range of about 96 to 180, a potential difference between the first common potential received when the first sub-pixel has the maximum brightness and the second common potential received when the second sub-pixel has the minimum brightness is in the range of about 0 mV to 100 mV.Type: GrantFiled: May 22, 2017Date of Patent: November 6, 2018Assignee: AU OPTRONICS CORPORATIONInventors: Yueh-Hung Chung, Hsueh-Ying Huang, Wei-Chun Wei, Shu-Cheng Kung, Ken-Yu Liu, Ya-Ling Hsu, Chen-Hsien Liao
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Publication number: 20180137827Abstract: A display device includes a first substrate, a second substrate, a display medium, a first pixel electrode, a second pixel electrode and a transparent electrode. Sub-pixel units are defined on the first substrate and the second substrate. A sub-pixel unit has a first sub-pixel and a second sub-pixel. The transparent electrode is disposed on the second substrate, and the transparent electrode receives a first common potential and a second common potential. When grey levels displayed by the first sub-pixel and the second sub-pixel are in the range of about 96 to 180, a potential difference between the first common potential received when the first sub-pixel has the maximum brightness and the second common potential received when the second sub-pixel has the minimum brightness is in the range of about 0 mV to 100 mV.Type: ApplicationFiled: May 22, 2017Publication date: May 17, 2018Inventors: Yueh-Hung CHUNG, Hsueh-Ying HUANG, Wei-Chun WEI, Shu-Cheng KUNG, Ken-Yu LIU, Ya-Ling HSU, Chen-Hsien LIAO
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Publication number: 20170337898Abstract: A display device having a light adjusting module and a control method thereof are provided. The display device includes a light source module, a light adjusting module, a display panel, and an eye detection device. The light source module has a light emitting surface. The light adjusting module has a plurality of predetermined positions, which is disposed on one side of the light source module corresponding to the light emitting surface. The display panel is disposed on the other side of the light adjusting module with respect to the light source module and has a display surface. The eye detection device is adjacent to the display surface for detecting an eye position of a user located in front of the display panel. The light adjusting module is capable of adjusting an optical property of the plurality of predetermined positions in accordance with the detected eye position and a light field of the light source module.Type: ApplicationFiled: May 4, 2017Publication date: November 23, 2017Inventors: Shu-Wen LIAO, Kuan-Yu Tung, Ken-Yu Liu
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Patent number: 9812397Abstract: In a method of fabricating a semiconductor device, an opening is formed inside a dielectric layer above a semiconductor substrate. The opening has a wall. At least one diffusion barrier material is then formed over the wall of the opening by at least two alternating steps, which are selected from the group consisting of a process of physical vapor deposition (PVD) and a process of atomic layer deposition (ALD). A liner layer is formed over the at least one diffusion barrier material.Type: GrantFiled: December 31, 2014Date of Patent: November 7, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kai-Shiang Kuo, Ken-Yu Chang, Ya-Lien Lee, Hung-Wen Su
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Publication number: 20170025378Abstract: In a method of bonding a bump of a bump of a semiconductor package, a semiconductor chip including the bump and a non-conductive film (NCF) may be on standby over a package substrate on a bonding stage. The semiconductor chip may be cooled. The semiconductor chip may be positioned on the package substrate. The semiconductor chip may be heated to a bonding temperature to bond the bump to the package substrate. Thus, the NCF of the semiconductor chip, which may be on standby at the buffer, may not be melt.Type: ApplicationFiled: April 8, 2016Publication date: January 26, 2017Inventor: Bong-Ken YU
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Patent number: 9437485Abstract: Semiconductor integrated circuit line structures for improving a process window in the vicinity of dense-to-isolated pattern transition areas and a technique to implement the line structures in the layout process are described in this disclosure. The disclosed structure includes a semiconductor substrate, and a material layer above the substrate. The material layer has a closely spaced dense line structure, an isolated line structure next to the dense line structure, and a dummy line shoulder structure formed in the vicinity of the dense line and the isolated line structures. One end of the dummy line shoulder structure connects to the isolated line structure and another end extends away from the isolated line structure in an orientation substantially perpendicular to the isolated line structure.Type: GrantFiled: April 4, 2014Date of Patent: September 6, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Cheng Kuo, Tzu-Chun Lo, Ming-Hsing Tsai, Ken-Yu Chang, Jye-Yen Cheng, Jeng-Shiun Ho, Hua-Tai Lin, Chih-Hsiang Yao
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Publication number: 20160126185Abstract: A method of forming a semiconductor structure includes the steps: providing a substrate; forming a dielectric over the substrate; forming an opening recessed under a top surface of the dielectric; forming a barrier layer on a sidewall of the opening; performing a physical vapor deposition (PVD) to form a copper layer over the barrier layer, a corner of the opening intersecting with the top surface and the top surface with a predetermined resputter ratio so that the ratio of the thickness of the copper layer on the barrier layer and the thickness of the copper layer over the top surface is substantially greater than 1.Type: ApplicationFiled: January 5, 2016Publication date: May 5, 2016Inventors: KEN-YU CHANG, HUNG-WEN SU
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Patent number: 9240378Abstract: A method of forming a semiconductor structure includes the steps: providing a substrate; forming a dielectric over the substrate; forming an opening recessed under a top surface of the dielectric; forming a barrier layer on a sidewall of the opening; performing a physical vapor deposition (PVD) to form a copper layer over the barrier layer, a corner of the opening intersecting with the top surface and the top surface with a predetermined resputter ratio so that the ratio of the thickness of the copper layer on the barrier layer and the thickness of the copper layer over the top surface is substantially greater than 1.Type: GrantFiled: May 16, 2014Date of Patent: January 19, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ken-Yu Chang, Hung-Wen Su
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Publication number: 20150333012Abstract: A method of forming a semiconductor structure includes the steps: providing a substrate; forming a dielectric over the substrate; forming an opening recessed under a top surface of the dielectric; forming a barrier layer on a sidewall of the opening; performing a physical vapor deposition (PVD) to form a copper layer over the barrier layer, a corner of the opening intersecting with the top surface and the top surface with a predetermined resputter ratio so that the ratio of the thickness of the copper layer on the barrier layer and the thickness of the copper layer over the top surface is substantially greater than 1.Type: ApplicationFiled: May 16, 2014Publication date: November 19, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: KEN-YU CHANG, HUNG-WEN SU
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Publication number: 20150108649Abstract: In a method of fabricating a semiconductor device, an opening is formed inside a dielectric layer above a semiconductor substrate. The opening has a wall. At least one diffusion barrier material is then formed over the wall of the opening by at least two alternating steps, which are selected from the group consisting of a process of physical vapor deposition (PVD) and a process of atomic layer deposition (ALD). A liner layer is formed over the at least one diffusion barrier material.Type: ApplicationFiled: December 31, 2014Publication date: April 23, 2015Inventors: Kai-Shiang KUO, Ken-Yu CHANG, Ya-Lien LEE, Hung-Wen SU
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Patent number: 8962473Abstract: In a method of fabricating a semiconductor device, an opening is formed inside a dielectric layer above a semiconductor substrate. The opening has a wall. At least one diffusion barrier material is then formed over the wall of the opening by at least two alternating steps, which are selected from the group consisting of a process of physical vapor deposition (PVD) and a process of atomic layer deposition (ALD). A liner layer is formed over the at least one diffusion barrier material.Type: GrantFiled: March 15, 2013Date of Patent: February 24, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kai-Shiang Kuo, Ken-Yu Chang, Ya-Lien Lee, Hung-Wen Su
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Publication number: 20140264867Abstract: In a method of fabricating a semiconductor device, an opening is formed inside a dielectric layer above a semiconductor substrate. The opening has a wall. At least one diffusion barrier material is then formed over the wall of the opening by at least two alternating steps, which are selected from the group consisting of a process of physical vapor deposition (PVD) and a process of atomic layer deposition (ALD). A liner layer is formed over the at least one diffusion barrier material.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kai-Shiang KUO, Ken-Yu CHANG, Ya-Lien LEE, Hung-Wen SU
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Patent number: 8823785Abstract: A display system including a display apparatus for displaying a first image and a second image, two first lenses and two second lenses is provided. When a viewer sees the display apparatus via one first lenses and one second lenses, and the first image as well as the second image are parallax images, the first and second images are respectively saw by different eyes of the viewer. When the viewer sees the display apparatus through the two first lenses, and the first image as well as the second image are not parallax images, the first image irrelevant to the second image is saw by the viewer. When the viewer sees the display apparatus through the two second lenses, and the first image as well as the second image are not parallax images, the second image irrelevant to the first image is saw by the viewer.Type: GrantFiled: March 1, 2011Date of Patent: September 2, 2014Assignee: Au Optronics CorporationInventors: Wei-Ching Hsu, Cheng-Han Tsao, Ken-Yu Liu, Chia-Chih Kao, Chao-Yuan Chen
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Publication number: 20140208283Abstract: Semiconductor integrated circuit line structures for improving a process window in the vicinity of dense-to-isolated pattern transition areas and a technique to implement the line structures in the layout process are described in this disclosure. The disclosed structure includes a semiconductor substrate, and a material layer above the substrate. The material layer has a closely spaced dense line structure, an isolated line structure next to the dense line structure, and a dummy line shoulder structure formed in the vicinity of the dense line and the isolated line structures. One end of the dummy line shoulder structure connects to the isolated line structure and another end extends away from the isolated line structure in an orientation substantially perpendicular to the isolated line structure.Type: ApplicationFiled: April 4, 2014Publication date: July 24, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Cheng Kuo, Tzu-Chun Lo, Ming-Hsing Tsai, Ken-Yu Chang, Jye-Yen Cheng, Jeng-Shiun Ho, Hua-Tai Lin, Chih-Hsiang Yao
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Modularized interface and related method for connecting plug-in electric vehicles to the energy grid
Patent number: 8736225Abstract: This invention is directed to a modularized interface for connecting a plug-in electric vehicle to the energy grid. For use with public or semi-public outlets, the modularized interface comprises a module and a smart socket, where the module is integrated within or capable of being connected to, the vehicle's charging interface. The module is normally disabled, but is enabled only after the end user is authenticated, the smart socket and its associated meter have been identified, and the module and the end user's account with the local utility are validated. The module meters the energy consumption, and, when the module is disconnected from the smart socket, indicating termination of the charging session, the metered data is communicated to the utility for updating the end user's account, and the module is disabled. The module is also capable of use with conventional outlets located, for example, in private residences.Type: GrantFiled: November 5, 2008Date of Patent: May 27, 2014Assignee: San Diego Gas & Electronic CompanyInventors: Chris W. Chen, Robert Peelle, Viral Bhalodia, Ken Yu, Gabriel Gavrielides, Terry Mohn, John C. Martin -
Patent number: 8692351Abstract: Semiconductor integrated circuit line structures for improving a process window in the vicinity of dense-to-isolated pattern transition areas and a technique to implement the line structures in the layout process are described in this disclosure. The disclosed structure includes a semiconductor substrate, and a material layer above the substrate. The material layer has a closely spaced dense line structure, an isolated line structure next to the dense line structure, and a dummy line shoulder structure formed in the vicinity of the dense line and the isolated line structures. One end of the dummy line shoulder structure connects to the isolated line structure and another end extends away from the isolated line structure in an orientation substantially perpendicular to the isolated line structure.Type: GrantFiled: April 2, 2010Date of Patent: April 8, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng Cheng Kuo, Luke Lo, Minghsing Tsai, Ken-Yu Chang, Jye-Yen Cheng, Jeng-Shiun Ho, Hua-Tai Lin, Chih-Hsiang Yao
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Patent number: 8552546Abstract: Provided is a semiconductor package. The semiconductor package may include a first semiconductor package having first semiconductor chips sequentially stacked on a substrate. In example embodiments, the first semiconductor chips may have a cascaded arrangement in which first sides and second sides of the semiconductor chips define cascade patterns. The cascaded arrangement may extend in a first direction to define a space between the first sides of the first semiconductor chips and the substrate. The semiconductor package may also include at least one first connection wiring at the second sides of the semiconductor chips, the at least one first connection wiring being configured to electrically connect the substrate with the first semiconductor chips. In addition, the semiconductor package may further include a first filling auxiliary structure adjacent to the first sides of the first semiconductor chips.Type: GrantFiled: October 1, 2010Date of Patent: October 8, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: In-Sang Song, Seok-Keun Lim, In-Wook Jung, Bong-Ken Yu, Sang-Wook Park, Ji-Seok Hong
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Patent number: 8456580Abstract: A three-dimensional display including a display panel and a phase retardation film is provided. The display panel has a plurality of first pixel regions and a plurality of second pixel regions arranged in arrays. The phase retardation film is configured on a surface of the display panel. Here, the phase retardation film has a plurality of first retardation regions and a plurality of second retardation regions that are arranged alternately. The first retardation regions have the same phase retardation, the second retardation regions have the same phase retardation, and the phase retardation of the first retardation regions is different from that of the second retardation regions. All the regions of the phase retardation film have the same optical transmittance. A displaying method adaptable to the three-dimensional display is also provided.Type: GrantFiled: May 16, 2011Date of Patent: June 4, 2013Assignee: Au Optronics CorporationInventors: Li Chen, Chia-Chih Kao, Chao-Yuan Chen, Ken-Yu Liu, Wen-Hao Hsu, Jenn-Jia Su
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Publication number: 20120169714Abstract: A display system including a display apparatus for displaying a first image and a second image, two first lenses and two second lenses is provided. When a viewer sees the display apparatus via one first lenses and one second lenses, and the first image as well as the second image are parallax images, the first and second images are respectively saw by different eyes of the viewer. When the viewer sees the display apparatus through the two first lenses, and the first image as well as the second image are not parallax images, the first image irrelevant to the second image is saw by the viewer. When the viewer sees the display apparatus through the two second lenses, and the first image as well as the second image are not parallax images, the second image irrelevant to the first image is saw by the viewer.Type: ApplicationFiled: March 1, 2011Publication date: July 5, 2012Applicant: Au Optronics CorporationInventors: Wei-Ching Hsu, Cheng-Han Tsao, Ken-Yu Liu, Chia-Chih Kao, Chao-Yuan Chen
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Patent number: 8139486Abstract: Described are a method and system for generating an asynchronous data frame. A character received from an asynchronous device is buffered. Each additional character from the asynchronous device is buffered if the additional character is received before the expiration of a predetermined interval measured from a time when a last buffered character was received. The one or more buffered characters are assembled as a data frame after the expiration of the predetermined interval if no additional character is received from the asynchronous device before the expiration of the predetermined interval. An encapsulated TCP packet that includes the data frame is generated for transmission across a TCP/IP network to a remote device.Type: GrantFiled: July 12, 2005Date of Patent: March 20, 2012Assignee: Avaya Inc.Inventors: Ken Yu, Shang Chang