Patents by Inventor Ken Yu
Ken Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210240222Abstract: An optical film includes a rough surface having multiple measuring points constituting multiple virtual measuring planes in a given unit measuring area. A normal to each virtual measuring plane has an angle with a normal to a reference plane. On the reference plane, the projection area of the virtual measuring planes having the angle larger than 20 degrees ranges from 31% to 60% of the projection area of the given unit measuring area. The projection area of the virtual measuring planes having the angle larger than 50 degrees is less than 7% of the projection area of the given unit measuring area. 25% of the measuring points has the height larger than a first height. 75% of the measuring points has the height larger than a second height. The first height and the second height have a difference not less than 0.6 ?m and not larger than 2.5 ?m.Type: ApplicationFiled: November 6, 2020Publication date: August 5, 2021Inventors: Shu-Cheng KUNG, Ken-Yu LIU, Kuan-Yu TUNG
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Publication number: 20210225701Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back. After etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. A conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.Type: ApplicationFiled: April 5, 2021Publication date: July 22, 2021Inventors: Yu Shih Wang, Chun-I Tsai, Shian Wei Mao, Ken-Yu Chang, Ming-Hsing Tsai, Wei-Jung Lin
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Patent number: 11062941Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.Type: GrantFiled: March 2, 2020Date of Patent: July 13, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ken-Yu Chang, Chun-I Tsai, Ming-Hsing Tsai, Wei-Jung Lin
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Patent number: 10971396Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back. After etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. A conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.Type: GrantFiled: November 29, 2018Date of Patent: April 6, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu Shih Wang, Chun-I Tsai, Shian Wei Mao, Ken-Yu Chang, Ming-Hsing Tsai, Wei-Jung Lin
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Patent number: 10964590Abstract: The present disclosure describes a method to a metallization process with improved gap fill properties. The method includes forming a contact opening in an oxide, forming a barrier layer in the contact opening, forming a liner layer on the barrier layer, and forming a first metal layer on the liner layer to partially fill the contact opening. The method further includes forming a second metal layer on the first metal layer to fill the contact opening, where forming the second metal layer includes sputter depositing the second metal layer with a first radio frequency (RF) power and a direct current power, as well as reflowing the second metal layer with a second RF power.Type: GrantFiled: April 30, 2018Date of Patent: March 30, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tien-Pei Chou, Ken-Yu Chang, Sheng-Hsuan Lin, Yueh-Ching Pai, Yu-Ting Lin
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Patent number: 10891135Abstract: A system and a method are disclosed to process instructions in an execution unit (EU) that includes an operand cache (OC). The OC stores a copy of at least one frequently used operand stored in a physical register file (PRF). The EU may process instructions using operands obtained from the PRF or from the OC. In the first mode, an OC renaming unit (OC-REN) indicates to the EU to process instructions using operands obtained from the OC if processing the instructions using operands obtained from the OC uses less power than using operands obtained from the PRF. In the second mode, the OC-REN indicates to the EU to process the instructions using operands obtained from the PRF if processing the instructions using operands obtained from the PRF uses less power than using operands obtained from the OC.Type: GrantFiled: March 6, 2019Date of Patent: January 12, 2021Inventors: Paul E. Kitchin, Nicholas Humphries, Ken Yu Lim, Ryan Hensley
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Publication number: 20200225954Abstract: A system and a method are disclosed to process instructions in an execution unit (EU) that includes an operand cache (OC). The OC stores a copy of at least one frequently used operand stored in a physical register file (PRF). The EU may process instructions using operands obtained from the PRF or from the OC. In the first mode, an OC renaming unit (OC-REN) indicates to the EU to process instructions using operands obtained from the OC if processing the instructions using operands obtained from the OC uses less power than using operands obtained from the PRF. In the second mode, the OC-REN indicates to the EU to process the instructions using operands obtained from the PRF if processing the instructions using operands obtained from the PRF uses less power than using operands obtained from the OC.Type: ApplicationFiled: March 6, 2019Publication date: July 16, 2020Inventors: Paul E. KITCHIN, Nicholas HUMPHRIES, Ken Yu LIM, Ryan HENSLEY
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Publication number: 20200203222Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.Type: ApplicationFiled: March 2, 2020Publication date: June 25, 2020Inventors: Ken-Yu Chang, Chun-I Tsai, Ming-Hsing Tsai, Wei-Jung Lin
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Publication number: 20200111739Abstract: A method for forming a semiconductor contact structure is provided. The method includes depositing a dielectric layer over a substrate. The method also includes etching the dielectric layer to expose a sidewall of the dielectric layer and a top surface of the substrate. In addition, the method includes forming a silicide region in the substrate. The method also includes applying a plasma treatment to the sidewall of the dielectric layer and the top surface of the substrate to form a nitridation region adjacent to a periphery of the silicide region. The method further includes depositing an adhesion layer on the dielectric layer and the silicide region.Type: ApplicationFiled: December 9, 2019Publication date: April 9, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Wen CHENG, Wei-Yip LOH, Yu-Hsiang LIAO, Sheng-Hsuan LIN, Hong-Mao LEE, Chun-I TSAI, Ken-Yu CHANG, Wei-Jung LIN, Chih-Wei CHANG, Ming-Hsing TSAI
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Patent number: 10580693Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.Type: GrantFiled: July 11, 2018Date of Patent: March 3, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ken-Yu Chang, Chun-I Tsai, Ming-Hsing Tsai, Wei-Jung Lin
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Publication number: 20200020578Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.Type: ApplicationFiled: July 11, 2018Publication date: January 16, 2020Inventors: Ken-Yu Chang, Chun-I Tsai, Ming-Hsing Tsai, Wei-Jung Lin
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Patent number: 10504832Abstract: A method of forming a semiconductor structure includes the steps: providing a substrate; forming a dielectric over the substrate; forming an opening recessed under a top surface of the dielectric; forming a barrier layer on a sidewall of the opening; performing a physical vapor deposition (PVD) to form a copper layer over the barrier layer, a corner of the opening intersecting with the top surface and the top surface with a predetermined resputter ratio so that the ratio of the thickness of the copper layer on the barrier layer and the thickness of the copper layer over the top surface is substantially greater than 1.Type: GrantFiled: January 5, 2016Date of Patent: December 10, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ken-Yu Chang, Hung-Wen Su
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Patent number: 10504834Abstract: A semiconductor device and method of forming the same that includes forming a dielectric layer over a substrate and patterning a contact region in the dielectric layer, the contact region having side portions and a bottom portion that exposes the substrate. The method can also include forming a dielectric barrier layer in the contact region to cover the side portions and the bottom portion, and etching the dielectric barrier layer to expose the substrate. Subsequently, a conductive layer can be formed to cover the side portions and the bottom portion of the contact region and the conductive layer can be annealed to form a silicide region in the substrate beneath the bottom portion of the contact region, and the conductive layer can then be selectively removed on the side portions of the contact region.Type: GrantFiled: March 1, 2018Date of Patent: December 10, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Wen Cheng, Wei-Yip Loh, Yu-Hsiang Liao, Sheng-Hsuan Lin, Hong-Mao Lee, Chun-I Tsai, Ken-Yu Chang, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
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Publication number: 20190273042Abstract: A semiconductor device and method of forming the same that includes forming a dielectric layer over a substrate and patterning a contact region in the dielectric layer, the contact region having side portions and a bottom portion that exposes the substrate. The method can also include forming a dielectric barrier layer in the contact region to cover the side portions and the bottom portion, and etching the dielectric barrier layer to expose the substrate. Subsequently, a conductive layer can be formed to cover the side portions and the bottom portion of the contact region and the conductive layer can be annealed to form a silicide region in the substrate beneath the bottom portion of the contact region, and the conductive layer can then be selectively removed on the side portions of the contact region.Type: ApplicationFiled: March 1, 2018Publication date: September 5, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Wen Cheng, Wei-Yip Loh, Yu-Hsiang Liao, Sheng-Hsuan Lin, Hong-Mao Lee, Chun-I Tsai, Ken-Yu Chang, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
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Patent number: 10361120Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back. After etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. A conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.Type: GrantFiled: January 25, 2018Date of Patent: July 23, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu Shih Wang, Chun-I Tsai, Shian Wei Mao, Ken-Yu Chang, Ming-Hsing Tsai, Wei-Jung Lin
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Patent number: 10332789Abstract: The present disclosure relates generally to techniques for forming a continuous adhesion layer for a contact plug. A method includes forming an opening through a dielectric layer to an active area on a substrate. The method includes performing a first plasma treatment along a sidewall of the opening. The method includes performing an atomic layer deposition (ALD) process to form a metal nitride layer along the sidewall of the opening. The ALD process includes a plurality of cycles. Each cycle includes flowing a precursor to form a metal monolayer along the sidewall and performing a second plasma treatment to treat the metal monolayer with nitrogen. The method includes depositing a conductive material on the metal nitride layer in the opening to form a conductive feature.Type: GrantFiled: February 2, 2018Date of Patent: June 25, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tien-Pei Chou, Ken-Yu Chang, Chun-Chieh Wang, Yueh-Ching Pai, Yu-Ting Lin, Yu-Wen Cheng
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Publication number: 20190164822Abstract: The present disclosure relates generally to techniques for forming a continuous adhesion layer for a contact plug. A method includes forming an opening through a dielectric layer to an active area on a substrate. The method includes performing a first plasma treatment along a sidewall of the opening. The method includes performing an atomic layer deposition (ALD) process to form a metal nitride layer along the sidewall of the opening. The ALD process includes a plurality of cycles. Each cycle includes flowing a precursor to form a metal monolayer along the sidewall and performing a second plasma treatment to treat the metal monolayer with nitrogen. The method includes depositing a conductive material on the metal nitride layer in the opening to form a conductive feature.Type: ApplicationFiled: February 2, 2018Publication date: May 30, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tien-Pei CHOU, Ken-Yu CHANG, Chun-Chieh WANG, Yueh-Ching PAI, Yu-Ting LIN, Yu-Wen CHENG
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Publication number: 20190164823Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back. After etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. A conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.Type: ApplicationFiled: January 25, 2018Publication date: May 30, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu Shih WANG, Chun-I TSAI, Shian Wei MAO, Ken-Yu CHANG, Ming-Hsing TSAI, Wei-Jung LIN
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Publication number: 20190164824Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back. After etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. A conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.Type: ApplicationFiled: November 29, 2018Publication date: May 30, 2019Inventors: Yu Shih Wang, Chun-I Tsai, Shian Wei Mao, Ken-Yu Chang, Ming-Hsing Tsai, Wei-Jung Lin
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Publication number: 20190148223Abstract: The present disclosure describes a method to a metallization process with improved gap fill properties. The method includes forming a contact opening in an oxide, forming a barrier layer in the contact opening, forming a liner layer on the barrier layer, and forming a first metal layer on the liner layer to partially fill the contact opening. The method further includes forming a second metal layer on the first metal layer to fill the contact opening, where forming the second metal layer includes sputter depositing the second metal layer with a first radio frequency (RF) power and a direct current power, as well as reflowing the second metal layer with a second RF power.Type: ApplicationFiled: April 30, 2018Publication date: May 16, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tien-Pei CHOU, Ken-Yu CHANG, Sheng-Hsuan LIN, Yueh-Ching PAI, Yu-Ting LIN