Patents by Inventor Keng-Chu Lin

Keng-Chu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Low-k interconnect structures with reduced RC delay
    Patent number: 9087877
    Abstract: A method for forming an integrated circuit includes forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, forming a dielectric barrier layer covering at least sidewalls of the opening, performing a treatment to improve a wetting ability of the dielectric barrier layer, and filling the opening with a conductive material, wherein the conductive material is in contact with the dielectric barrier layer.
    Type: Grant
    Filed: October 24, 2006
    Date of Patent: July 21, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chi Ko, Ting-Yu Shen, Keng-Chu Lin, Chia-Cheng Chou, Tien-I Bao, Shwang-Ming Jeng, Chen-Hua Yu
  • Method of forming a high density dielectric etch-stop layer
    Patent number: 9076845
    Abstract: A method of manufacturing an integrated circuit device includes forming an inter-level dielectric layer over a semiconductor substrate, forming a transformative layer over the inter-level dielectric layer, forming a protective layer over the transformative layer without allowing the transformative layer to undergo a substantive transformation, and after forming the protective layer, causing the transformative layer to undergo a volume-increasing transformation. The volume-increasing transformation produces a high density material that provides an effective etch stop.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: July 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Joung-Wei Liou, Han-Ti Hsiaw, Keng-Chu Lin
  • Hard mask for back-end-of-line (BEOL) interconnect structure
    Patent number: 9059259
    Abstract: A method of fabricating an interconnect structure on a wafer and an interconnect structure are provided. A dielectric layer is provided on the wafer. An interconnect is formed by etching a recess into the dielectric layer, where the etching utilizes a hard mask that includes a first layer deposited over the dielectric layer. The interconnect is planarized using a chemical mechanical polishing (CMP) process, where the first layer remains on the dielectric layer at a completion of the CMP process. The first layer or a portion of the first layer is transformed into a nitride layer or an oxide layer after the CMP process.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: June 16, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Joung-Wei Liou, Han-Ti Hsiaw, Keng-Chu Lin
  • Low-K dielectric layer and porogen
    Patent number: 9054110
    Abstract: A system and method for a low-k dielectric layer are provided. A preferred embodiment comprises forming a matrix and forming a porogen within the matrix. The porogen comprises an organic ring structure with fewer than fifteen carbons and a large percentage of single bonds. Additionally, the porogen may have a viscosity greater than 1.3 and a Reynolds numbers less than 0.5.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: June 9, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Joung-Wei Liou, Hui-Chun Yang, Yu-Yun Peng, Keng-Chu Lin
  • Method of and apparatus for active energy assist baking
    Patent number: 9004914
    Abstract: An Active Energy Assist (AEA) baking chamber includes an AEA light source assembly and a heater pedestal. The AEA baking chamber further includes a controller for controlling a power input to the AEA light source assembly and a power input to the heater pedestal. A method of forming interconnects on a substrate includes etching a substrate and wet cleaning the etched substrate. The method further includes active energy assist (AEA) baking the substrate after the wet-cleaning. The AEA baking includes placing the substrate on a heater pedestal in an AEA chamber, exposing the substrate to light having a wavelength equal to or greater than 400 nm, wherein said light is emitted by a light source and controlling the light source and the heater pedestal using a controller.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chi Ko, Chia Cheng Chou, Keng-Chu Lin, Joung-Wei Liou, Shwang-Ming Jeng, Mei-Ling Chen
  • High Density Dielectric Etch Stop Layer
    Publication number: 20150097288
    Abstract: A method of manufacturing an integrated circuit device includes forming an inter-level dielectric layer over a semiconductor substrate, forming a transformative layer over the inter-level dielectric layer, forming a protective layer over the transformative layer without allowing the transformative layer to undergo a substantive transformation, and after forming the protective layer, causing the transformative layer to undergo a volume-increasing transformation. The volume-increasing transformation produces a high density material that provides an effective etch stop.
    Type: Application
    Filed: October 3, 2013
    Publication date: April 9, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Joung-Wei Liou, Han-Ti Hsiaw, Keng-Chu Lin
  • Low-k Cu barriers in damascene interconnect structures
    Patent number: 8993435
    Abstract: In the formation of an interconnect structure, a metal feature is formed in a dielectric layer. An etch stop layer (ESL) is formed over the metal feature and the dielectric layer using a precursor and a carbon-source gas including carbon as precursors. The carbon-source gas is free from carbon dioxide (CO2). The precursor is selected from the group consisting essentially of 1-methylsilane (1MS), 2-methylsilane (2MS), 3-methylsilane (3MS), 4-methylsilane (4MS), and combinations thereof.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Chen Wang, Po-Cheng Shih, Chung-Chi Ko, Keng-Chu Lin, Shwang-Ming Jeng
  • Photoresist and Method of Formation and Use
    Publication number: 20150056555
    Abstract: A system and method for depositing a photoresist and utilizing the photoresist are provided. In an embodiment a deposition chamber is utilized along with a first precursor material comprising carbon-carbon double bonds and a second precursor material comprising repeating units to deposit the photoresist onto a substrate. The first precursor material is turned into a plasma in a remote plasma chamber prior to being introduced into the deposition chamber. The resulting photoresist comprises a carbon backbone with carbon-carbon double bonds.
    Type: Application
    Filed: August 22, 2013
    Publication date: February 26, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Keng-Chu Lin, Joung-Wei Liou, Cheng-Han Wu, Ya Hui Chang
  • Semiconductor Devices, Methods of Manufacture Thereof, and Inter-metal Dielectric (IMD) Structures
    Publication number: 20150048488
    Abstract: Semiconductor devices, methods of manufacture thereof, and IMD structures are disclosed. In some embodiments, a semiconductor device includes an adhesion layer disposed over a workpiece. The adhesion layer has a dielectric constant of about 4.0 or less and includes a substantially homogeneous material. An insulating material layer is disposed over the adhesion layer. The insulating material layer has a dielectric constant of about 2.6 or less. The adhesion layer and the insulating material layer comprise an IMD structure.
    Type: Application
    Filed: August 15, 2013
    Publication date: February 19, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Yun Peng, Keng-Chu Lin, Joung-Wei Liou, Kuang-Yuan Hsu
  • Apparatus and Methods for Low K Dielectric Layers
    Publication number: 20150041964
    Abstract: Methods and apparatus for a low k dielectric layer of porous SiCOH. A method includes placing a semiconductor substrate into a vapor deposition chamber; introducing reactive gases into the vapor deposition chamber to form a dielectric film comprising SiCOH and a decomposable porogen; depositing the dielectric film to have a ratio of Si—CH3 to SiOnetwork bonds of less than or equal to 0.25; and performing a cure for a cure time to remove substantially all of the porogen from the dielectric film. In one embodiment the porogen comprises a cyclic hydrocarbon. The porogen may be UV curable. In embodiments, different lowered Si—CH3 to SiOnetwork ratios for the deposition of the dielectric film are disclosed. An apparatus of a semiconductor device including the low k dielectric layers is disclosed.
    Type: Application
    Filed: October 24, 2014
    Publication date: February 12, 2015
    Inventors: Yu-Yun Peng, Keng-Chu Lin, Joung-Wei Liou, Hui-Chun Yang
  • Double patterning strategy for contact hole and trench in photolithography
    Patent number: 8940643
    Abstract: A method of lithography patterning includes forming a first etch stop layer, a second etch stop layer, and a hard mask layer on a material layer. The materials of the first etch stop layer and the second etch stop layer are selected by the way that there is a material gradient composition between the second etch stop layer, the first etch stop layer, and the material layer. Hence, gradient etching rates between the second etch stop layer, the first etch stop layer, and the material layer are achieved in an etching process to form etched patterns with smooth and/or vertical sidewalls within the second and the first etch stop layers and the material layer.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chi Ko, Chih-Hao Chen, Keng-Chu Lin
  • HARD MASK FOR BACK-END-OF-LINE (BEOL) INTERCONNECT STRUCTURE
    Publication number: 20150021779
    Abstract: A method of fabricating an interconnect structure on a wafer and an interconnect structure are provided. A dielectric layer is provided on the wafer. An interconnect is formed by etching a recess into the dielectric layer, where the etching utilizes a hard mask that includes a first layer deposited over the dielectric layer. The interconnect is planarized using a chemical mechanical polishing (CMP) process, where the first layer remains on the dielectric layer at a completion of the CMP process. The first layer or a portion of the first layer is transformed into a nitride layer or an oxide layer after the CMP process.
    Type: Application
    Filed: July 19, 2013
    Publication date: January 22, 2015
    Inventors: JOUNG-WEI LIOU, HAN-TI HSIAW, KENG-CHU LIN
  • BACK-END-OF-LINE (BEOL) INTERCONNECT STRUCTURE
    Publication number: 20150021770
    Abstract: A method of fabricating an interconnect structure on a wafer and an interconnect structure are provided. A dielectric layer is provided on the wafer, with the dielectric layer having a recess therein. A silicon (Si) layer is deposited in the recess. An interconnect is formed by providing a barrier layer and a conductive layer in the recess over the Si layer. The Si layer has a density that prevents or substantially prevents the barrier layer from moving away from the conductive layer and towards the dielectric layer during subsequent processing of the interconnect structure.
    Type: Application
    Filed: July 16, 2013
    Publication date: January 22, 2015
    Inventors: JOUNG-WEI LIOU, KENG-CHU LIN
  • Mechanism of forming semiconductor device having support structure
    Patent number: 8927420
    Abstract: Among other things, one or more support structures and techniques for forming such support structures within semiconductor devices are provided. The support structure comprises an oxide infused silicon layer that is formed within a trench of a dielectric layer on a substrate of a semiconductor device. The oxide infused silicon layer results from a silicon layer that is exposed to oxide during an ultraviolet (UV) curing process. The oxide infused silicon layer is configured to support a barrier layer against a conductive structure formed on the barrier layer within the trench. In this way, the support structure provides pressure against the barrier layer so that the barrier layer substantially maintains contact with the conductive structure, to promote improved performance and reliability of the conductive structure.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Joung-Wei Liou, Keng-Chu Lin
  • Apparatus and methods for low K dielectric layers
    Patent number: 8889567
    Abstract: Methods and apparatus for a low k dielectric layer of porous SiCOH. A method includes placing a semiconductor substrate into a vapor deposition chamber; introducing reactive gases into the vapor deposition chamber to form a dielectric film comprising SiCOH and a decomposable porogen; depositing the dielectric film to have a ratio of Si—CH3 to SiOnetwork bonds of less than or equal to 0.25; and performing a cure for a cure time to remove substantially all of the porogen from the dielectric film. In one embodiment the porogen comprises a cyclic hydrocarbon. The porogen may be UV curable. In embodiments, different lowered Si—CH3 to SiOnetwork ratios for the deposition of the dielectric film are disclosed. An apparatus of a semiconductor device including the low k dielectric layers is disclosed.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: November 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Yun Peng, Keng-Chu Lin, Joung-Wei Liou, Hui-Chun Yang
  • Curing low-k dielectrics for improving mechanical strength
    Patent number: 8853858
    Abstract: An integrated circuit structure including reflective metal pads is provided. The integrated circuit structure includes a semiconductor substrate; a first low-k dielectric layer overlying the semiconductor substrate, wherein the first low-k dielectric layer is a top low-k dielectric layer; a second low-k dielectric layer immediately underlying the first low-k dielectric layer; and a reflective metal pad in the second low-k dielectric layer.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: October 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Joung-Wei Liou, Keng-Chu Lin, Shwang-Ming Jeng
  • Method of modifying a low k dielectric layer having etched features and the resulting product
    Patent number: 8846528
    Abstract: A dielectric layer having features etched thereon and a low dielectric constant, and that is carried by a semiconductor substrate. The etched dielectric layer is modified so its surface energy is reduced by at least one of: (a) applying thermal energy to the layer to cause the layer temperature to be between 100 C and 400 C; (b) irradiating the layer with electromagnetic energy; and/or (c) irradiating the layer with free ions.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Joung-Wei Liou, Chung-Chi Ko, Chia-Cheng Chou, Keng-Chu Lin
  • PUMPING LINER FOR CHEMICAL VAPOR DEPOSITION
    Publication number: 20140261176
    Abstract: One or more pumping liners are provided for use in chemical vapor deposition (CVD). A pumping liner encircles a deposition chamber within which a wafer is placed and into which a precursor is introduced to form a thin film on a surface of the wafer. The pumping liner regulates a rate and uniformity at which a gas is removed from the deposition chamber, which in turn affects a duration or degree to which different portions of the wafer are exposed to the precursor. Controlling exposure of the wafer to the precursor promotes uniformity of the film formed on the wafer as well an ability to regulate the thickness of the film formed on the wafer. In an embodiment, a pumping liner has at least one of relatively small liner apertures, an increased number of liner apertures or a non-uniform distribution of liner apertures within a body of the pumping liner.
    Type: Application
    Filed: March 6, 2014
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Cheng-Hsiung Liu, Chun-Hao Hsu, Yu-Yun Peng, Chih-Yuan Yao, Chia-I Shen, Keng-Chu Lin
  • SUPPORT STRUCTURE FOR BARRIER LAYER OF SEMICONDUCTOR DEVICE
    Publication number: 20140217589
    Abstract: Among other things, one or more support structures and techniques for forming such support structures within semiconductor devices are provided. The support structure comprises an oxide infused silicon layer that is formed within a trench of a dielectric layer on a substrate of a semiconductor device. The oxide infused silicon layer results from a silicon layer that is exposed to oxide during an ultraviolet (UV) curing process. The oxide infused silicon layer is configured to support a barrier layer against a conductive structure formed on the barrier layer within the trench. In this way, the support structure provides pressure against the barrier layer so that the barrier layer substantially maintains contact with the conductive structure, to promote improved performance and reliability of the conductive structure.
    Type: Application
    Filed: February 4, 2013
    Publication date: August 7, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Joung-Wei Liou, Keng-Chu Lin
  • Method for forming self-assembled mono-layer liner for cu/porous low-k interconnections
    Patent number: 8629056
    Abstract: A method for fabricating an integrated circuit comprises forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, and treating the low-k dielectric layer with a gaseous organic chemical to cause a reaction between the low-k dielectric layer and the gaseous organic chemical. The gaseous organic chemical is free from silicon.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: January 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chi Ko, Chia-Cheng Chou, Keng-Chu Lin, Tien-I Bao, Chen-Hua Yu