Patents by Inventor Keng-Chu Lin

Keng-Chu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Double Patterning Strategy for Contact Hole and Trench in Photolithography
    Publication number: 20130337651
    Abstract: A method of lithography patterning includes forming a first etch stop layer, a second etch stop layer, and a hard mask layer on a material layer. The materials of the first etch stop layer and the second etch stop layer are selected by the way that there is a material gradient composition between the second etch stop layer, the first etch stop layer, and the material layer. Hence, gradient etching rates between the second etch stop layer, the first etch stop layer, and the material layer are achieved in an etching process to form etched patterns with smooth and/or vertical sidewalls within the second and the first etch stop layers and the material layer.
    Type: Application
    Filed: August 20, 2013
    Publication date: December 19, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chi Ko, Chih-Hao Chen, Keng-Chu Lin
  • Semiconductor Devices, Methods of Manufacture Thereof, and Methods of Forming Conductive Features
    Publication number: 20130277853
    Abstract: Semiconductor devices, methods of manufacture thereof, and methods of forming conductive features thereof are disclosed. A semiconductor device includes an insulating material layer disposed over a workpiece. The insulating material layer includes a silicon-containing material comprising about 13% or greater of carbon (C). A conductive feature is disposed within the insulating material layer. The conductive feature includes a capping layer disposed on a top surface thereof.
    Type: Application
    Filed: April 20, 2012
    Publication date: October 24, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hui-Chun Yang, Mei-Ling Chen, Keng-Chu Lin, Joung-Wei Liou
  • METHOD OF AND APPARATUS FOR ACTIVE ENERGY ASSIST BAKING
    Publication number: 20130273732
    Abstract: An Active Energy Assist (AEA) baking chamber includes an AEA light source assembly and a heater pedestal. The AEA baking chamber further includes a controller for controlling a power input to the AEA light source assembly and a power input to the heater pedestal. A method of forming interconnects on a substrate includes etching a substrate and wet cleaning the etched substrate. The method further includes active energy assist (AEA) baking the substrate after the wet-cleaning. The AEA baking includes placing the substrate on a heater pedestal in an AEA chamber, exposing the substrate to light having a wavelength equal to or greater than 400 nm, wherein said light is emitted by a light source and controlling the light source and the heater pedestal using a controller.
    Type: Application
    Filed: June 11, 2013
    Publication date: October 17, 2013
    Inventors: Chung-Chi KO, Chia Cheng CHOU, Keng-Chu LIN, Joung-Wei LIOU, Shwang-Ming JENG, Mei-Ling CHEN
  • Double patterning strategy for contact hole and trench in photolithography
    Patent number: 8536064
    Abstract: A method of lithography patterning includes forming a first etch stop layer, a second etch stop layer, and a hard mask layer on a material layer. The materials of the first etch stop layer and the second etch stop layer are selected by the way that there is a material gradient composition between the second etch stop layer, the first etch stop layer, and the material layer. Hence, gradient etching rates between the second etch stop layer, the first etch stop layer, and the material layer are achieved in an etching process to form etched patterns with smooth and/or vertical sidewalls within the second and the first etch stop layers and the material layer.
    Type: Grant
    Filed: February 8, 2010
    Date of Patent: September 17, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chi Ko, Chih-Hao Chen, Keng-Chu Lin
  • Method of and apparatus for active energy assist baking
    Patent number: 8481412
    Abstract: A method of and apparatus for forming interconnects on a substrate includes etching patterns in ultra-low k dielectric and removing moisture from the ultra-low k dielectric using active energy assist baking. During active energy assist baking, the ultra-low k dielectric is heated and exposed to light having only wavelengths greater than 400 nm for about 1 to about 20 minutes at a temperature of about 300 to about 400 degrees Celsius. The active energy assist baking is performed after wet-cleaning or after chemical mechanical polishing, or both.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: July 9, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chi Ko, Chia Cheng Chou, Keng-Chu Lin, Joung-Wei Liou, Shwang-Ming Jeng, Mei-Ling Chen
  • Double patterning strategy for contact hole and trench in photolithography
    Patent number: 8470708
    Abstract: A method of lithography patterning includes forming a mask layer on a material layer and forming a capping layer on the mask layer. The capping layer is a boron-containing layer with a higher resistance to an etching reaction of patterning process of the material layer. By adapting the boron-containing layer as the capping layer, the thickness of the mask layer can be thus reduced. Hence, a better gap filling for forming an interconnect metallization in the material layer could be achieved as well.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: June 25, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Cheng Shih, Kuan-Chen Wang, Chung-Chi Ko, Keng-Chu Lin, Tai-Yen Peng, Wen-Kuo Hsieh, Chih-Hao Chen
  • METHOD OF MODIFYING A LOW K DIELECTRIC LAYER HAVING ETCHED FEATURES AND THE RESULTING PRODUCT
    Publication number: 20130137261
    Abstract: A dielectric layer having features etched thereon and a low dielectric constant, and that is carried by a semiconductor substrate. The etched dielectric layer is modified so its surface energy is reduced by at least one of: (a) applying thermal energy to the layer to cause the layer temperature to be between 100 C and 400 C; (b) irradiating the layer with electromagnetic energy; and/or (c) irradiating the layer with free ions.
    Type: Application
    Filed: November 29, 2011
    Publication date: May 30, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Joung-Wei LIOU, Chung-Chi KO, Chia-Cheng CHOU, Keng-Chu LIN
  • Apparatus and Methods for Low K Dielectric Layers
    Publication number: 20130072031
    Abstract: Methods and apparatus for a low k dielectric layer of porous SiCOH. A method includes placing a semiconductor substrate into a vapor deposition chamber; introducing reactive gases into the vapor deposition chamber to form a dielectric film comprising SiCOH and a decomposable porogen; depositing the dielectric film to have a ratio of Si—CH3 to SiOnetwork bonds of less than or equal to 0.25; and performing a cure for a cure time to remove substantially all of the porogen from the dielectric film. In one embodiment the porogen comprises a cyclic hydrocarbon. The porogen may be UV curable. In embodiments, different lowered Si—CH3 to SiOnetwork ratios for the deposition of the dielectric film are disclosed. An apparatus of a semiconductor device including the low k dielectric layers is disclosed.
    Type: Application
    Filed: September 16, 2011
    Publication date: March 21, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Yun Peng, Keng-Chu Lin, Joung-Wei Liou, Hui-Chun Yang
  • Semiconductor Device and Method for Forming the Same
    Publication number: 20130062774
    Abstract: A method includes forming a metal hard mask over a low-k dielectric layer. The step of forming the metal hard mask includes depositing a sub-layer of the metal hard mask, and performing a plasma treatment on the sub-layer of the metal hard mask. The metal hard mask is patterned to form an opening. The low-k dielectric layer is etched to form a trench, wherein the step of etching is performed using the metal hard mask as an etching mask.
    Type: Application
    Filed: September 8, 2011
    Publication date: March 14, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chi Ko, Chia-Cheng Chou, Shing-Chyang Pan, Keng-Chu Lin, Shwang-Ming Jeng
  • Methods for Forming Interconnect Structures of Integrated Circuits
    Publication number: 20130052818
    Abstract: A method includes forming a hard mask over a low-k dielectric layer, and patterning the hard mask to form an opening. A stress tuning layer is formed over the low-k dielectric layer and in physical contact with the hard mask. The stress tuning layer has an inherent stress, wherein the inherent stress is a near-zero stress or a tensile stress. The low-k dielectric layer is etched to form a trench aligned to the opening, wherein the step of etching is performed using the hard mask as an etching mask.
    Type: Application
    Filed: August 29, 2011
    Publication date: February 28, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Cheng Shih, Chung-Chi Ko, Keng-Chu Lin
  • Automatically adjusting baking process for low-k dielectric material
    Publication number: 20130052755
    Abstract: A method includes etching a low-k dielectric layer on a wafer to form an opening in the low-k dielectric layer. An amount of a detrimental substance in the wafer is measured to obtain a measurement result. Process conditions for baking the wafer are determined in response to the measurement result. The wafer is baked using the determined process conditions.
    Type: Application
    Filed: August 26, 2011
    Publication date: February 28, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chou, Chung-Chi Ko, Keng-Chu Lin, Shwang-Ming Jeng
  • Low-K Dielectric Layer and Porogen
    Publication number: 20130032955
    Abstract: A system and method for a low-k dielectric layer are provided. A preferred embodiment comprises forming a matrix and forming a porogen within the matrix. The porogen comprises an organic ring structure with fewer than fifteen carbons and a large percentage of single bonds. Additionally, the porogen may have a viscosity greater than 1.3 and a Reynolds numbers less than 0.5.
    Type: Application
    Filed: August 5, 2011
    Publication date: February 7, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Joung-Wei Liou, Hui-Chun Yang, Yu-Yun Peng, Keng-Chu Lin
  • Method for fabricating low-k dielectric and Cu interconnect
    Patent number: 8354346
    Abstract: A system and method for improving the performance of an integrated circuit by lowering RC delay time is provided. A preferred embodiment comprises adding a reactive etch gas to the ash/flush plasma process following a low-k dielectric etch. The illustrative embodiments implement a removal of the damage layer that is formed during a low-k dielectric etch.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: January 15, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Chia-Cheng Chou, Ming-Chung Liang, Keng-Chu Lin, Tzu-Li Lee
  • Curing Low-k Dielectrics for Improving Mechanical Strength
    Publication number: 20120306098
    Abstract: An integrated circuit structure including reflective metal pads is provided. The integrated circuit structure includes a semiconductor substrate; a first low-k dielectric layer overlying the semiconductor substrate, wherein the first low-k dielectric layer is a top low-k dielectric layer; a second low-k dielectric layer immediately underlying the first low-k dielectric layer; and a reflective metal pad in the second low-k dielectric layer.
    Type: Application
    Filed: August 9, 2012
    Publication date: December 6, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Joung-Wei Liou, Keng-Chu Lin, Shwang-Ming Jeng
  • Curing low-k dielectrics for improving mechanical strength
    Patent number: 8258629
    Abstract: An integrated circuit structure including reflective metal pads is provided. The integrated circuit structure includes a semiconductor substrate; a first low-k dielectric layer overlying the semiconductor substrate, wherein the first low-k dielectric layer is a top low-k dielectric layer; a second low-k dielectric layer immediately underlying the first low-k dielectric layer; and a reflective metal pad in the second low-k dielectric layer.
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: September 4, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Joung-Wei Liou, Keng-Chu Lin, Shwang-Ming Jeng
  • METHOD OF AND APPARATUS FOR ACTIVE ENERGY ASSIST BAKING
    Publication number: 20120077339
    Abstract: A method of and apparatus for forming interconnects on a substrate includes etching patterns in ultra-low k dielectric and removing moisture from the ultra-low k dielectric using active energy assist baking. During active energy assist baking, the ultra-low k dielectric is heated and exposed to light having only wavelengths greater than 400 nm for about 1 to about 20 minutes at a temperature of about 300 to about 400 degrees Celsius. The active energy assist baking is performed after wet-cleaning or after chemical mechanical polishing, or both.
    Type: Application
    Filed: September 29, 2010
    Publication date: March 29, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Chi KO, Chia Cheng CHOU, Keng-Chu LIN, Joung-Wei LIOU, Shwang-Ming JENG, Mei-Ling CHEN
  • Post etch dielectric film re-capping layer
    Patent number: 8105947
    Abstract: Methods for improving post etch in via or trench formation in semiconductor devices. A preferred embodiment comprises forming a re-capping layer over a dielectric film following an initial etch to form a feature in the dielectric film, followed by additional etch and etch back processing steps. The re-capping method provides protection for underlying films and prevents film damage post etch. Uniform feature profiles are maintained and critical dimension uniformity is obtained by use of the methods of the invention. The time dependent dielectric breakdown performance is increased.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: January 31, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shwang-Ming Jeng, Kin-Weng Wang, Hsin-Yi Tsai, Keng-Chu Lin, Chung-Chi Ko
  • Method for Fabricating Low-k Dielectric and Cu Interconnect
    Publication number: 20110263127
    Abstract: A system and method for improving the performance of an integrated circuit by lowering RC delay time is provided. A preferred embodiment comprises adding a reactive etch gas to the ash/flush plasma process following a low-k dielectric etch. The illustrative embodiments implement a removal of the damage layer that is formed during a low-k dielectric etch.
    Type: Application
    Filed: July 8, 2011
    Publication date: October 27, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Chia-Cheng Chou, Ming-Chung Liang, Keng-Chu Lin, Tzu-Li Lee
  • Low-k Cu Barriers in Damascene Interconnect Structures
    Publication number: 20110223759
    Abstract: In the formation of an interconnect structure, a metal feature is formed in a dielectric layer. An etch stop layer (ESL) is formed over the metal feature and the dielectric layer using a precursor and a carbon-source gas including carbon as precursors. The carbon-source gas is free from carbon dioxide (CO2). The precursor is selected from the group consisting essentially of 1-methylsilane (1MS), 2-methylsilane (2MS), 3-methylsilane (3MS), 4-methylsilane (4MS), and combinations thereof.
    Type: Application
    Filed: March 15, 2010
    Publication date: September 15, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Chen Wang, Po-Cheng Shih, Chung-Chi Ko, Keng-Chu Lin, Shwang-Ming Jeng
  • Method for Forming Self-Assembled Mono-Layer Liner for Cu/Porous Low-k Interconnections
    Publication number: 20110217840
    Abstract: A method for fabricating an integrated circuit comprises forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, and treating the low-k dielectric layer with a gaseous organic chemical to cause a reaction between the low-k dielectric layer and the gaseous organic chemical. The gaseous organic chemical is free from silicon.
    Type: Application
    Filed: May 13, 2011
    Publication date: September 8, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chi Ko, Chia-Cheng Chou, Keng-Chu Lin, Tien-I Bao, Chen-Hua Yu