Patents by Inventor Keng-Chu Lin

Keng-Chu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DEVICE AND METHOD OF DIELECTRIC LAYER
    Publication number: 20190267485
    Abstract: A device includes a semiconductor substrate, a gate stack, and an interlayer dielectric. The gate stack is over the semiconductor substrate. The interlayer dielectric is over the semiconductor substrate and surrounds the gate stack. The interlayer dielectric includes a liner layer and a filling layer. The liner layer lines the gate stack. The filling layer is over the liner layer and includes a metal-contained ternary dielectric material.
    Type: Application
    Filed: May 13, 2019
    Publication date: August 29, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Yun PENG, Keng-Chu LIN
  • Interconnect Structures and Methods of Forming the Same
    Publication number: 20190214296
    Abstract: Embodiments described herein relate generally to one or more methods for forming an interconnect structure, such as a dual damascene interconnect structure comprising a conductive line and a conductive via, and structures formed thereby. In some embodiments, an interconnect opening is formed through one or more dielectric layers over a semiconductor substrate. The interconnect opening has a via opening and a trench over the via opening. A conductive via is formed in the via opening. A nucleation enhancement treatment is performed on one or more exposed dielectric surfaces of the trench. A conductive line is formed in the trench on the one or more exposed dielectric surfaces of the trench and on the conductive via.
    Type: Application
    Filed: March 15, 2019
    Publication date: July 11, 2019
    Inventors: Sung-Li Wang, Shuen-Shin Liang, Jung-Hao Chang, Chia-Hung Chu, Keng-Chu Lin
  • LUMINESCENT MATERIAL AND LIGHT EMITTING DEVICE AND DISPLAY DEVICE USING THE SAME
    Publication number: 20190181306
    Abstract: A luminescent material, a light emitting device, and a display device are disclosed. The luminescent material includes particles and a phosphor. The particles include quantum dots and have an average diameter of 0.06 ?m to 30 ?m.
    Type: Application
    Filed: November 21, 2018
    Publication date: June 13, 2019
    Inventors: Yuan-Ren JUANG, Szu-Chun YU, Keng-Chu LIN, Wei-Ta CHEN, Yao-Tsung CHUANG, Jen-Shrong UEN
  • LUMINESCENT MATERIAL AND ELECTRONIC DEVICE HAVING A DISPLAY FUNCTION USING THE SAME
    Publication number: 20190177612
    Abstract: A luminescent material includes a particle of an irregular shape. The particle of an irregular shape includes a core of an irregular shape and quantum dots. The quantum dots distribute on the core.
    Type: Application
    Filed: November 8, 2018
    Publication date: June 13, 2019
    Inventors: Yuan-Ren JUANG, Szu-Chun YU, Keng-Chu LIN, Wei-Ta CHEN, Yao-Tsung CHUANG, Jen-Shrong UEN
  • Forming interconnect structure using plasma treated metal hard mask
    Patent number: 10312107
    Abstract: A method includes forming a metal hard mask over a low-k dielectric layer. The step of forming the metal hard mask includes depositing a sub-layer of the metal hard mask, and performing a plasma treatment on the sub-layer of the metal hard mask. The metal hard mask is patterned to form an opening. The low-k dielectric layer is etched to form a trench, wherein the step of etching is performed using the metal hard mask as an etching mask.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: June 4, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chi Ko, Chia-Cheng Chou, Shing-Chyang Pan, Keng-Chu Lin, Shwang-Ming Jeng
  • SEMICONDUCTOR DEVICE
    Publication number: 20190165127
    Abstract: A semiconductor device is disclosed that includes a plurality of isolation regions. A fin is arranged between the plurality of isolation regions. One of the plurality of isolation regions includes a first atomic layer deposition (ALD) layer, a second ALD layer, a flowable chemical vapor deposition (FCVD) layer, and a third ALD layer. The first ALD layer includes a first trench. The second ALD layer is formed in the first trench of the first ALD layer. The FCVD layer is formed in the first trench of the first ALD layer and on the second ALD layer. The third ALD layer is formed on the FCVD layer.
    Type: Application
    Filed: January 30, 2018
    Publication date: May 30, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng CHING, Kuan-Lun CHENG, Chih-Hao WANG, Keng-Chu LIN, Shi-Ning JU
  • Device and method of dielectric layer
    Patent number: 10290739
    Abstract: A method includes etching a semiconductor substrate to form a trench extending from a top surface of the semiconductor substrate into the semiconductor substrate. A first liner layer is formed on sidewalls and a bottom of the trench. The trench is filled with a dielectric material after depositing the first liner layer. The dielectric material and the first liner layer include substantially the same metal-contained ternary dielectric material. Excess portions of the dielectric material and the first liner layer over the top surface of the semiconductor substrate are removed.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: May 14, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Yun Peng, Keng-Chu Lin
  • QUANTUM DOT, LIGHT EMITTING MATERIAL AND MANUFACTURING METHOD OF QUANTUM DOT
    Publication number: 20190119568
    Abstract: A quantum dot, a light emitting material, and a manufacturing method of quantum dot are provided. A ratio of an emission intensity to an absorption intensity of the quantum dot at a characteristic wavelength ranges from 1.5×108 CPS/Abs. to 2.0×109 CPS/Abs. The characteristic wavelength is a shorter wavelength of two wavelengths corresponding to half of a maximum intensity of an emission peak of the quantum dot.
    Type: Application
    Filed: October 22, 2018
    Publication date: April 25, 2019
    Applicant: Chi Mei Corporation
    Inventor: Keng-Chu Lin
  • DEVICE AND METHOD OF DIELECTRIC LAYER
    Publication number: 20190103485
    Abstract: A method includes etching a semiconductor substrate to form a trench extending from a top surface of the semiconductor substrate into the semiconductor substrate. A first liner layer is formed on sidewalls and a bottom of the trench. The trench is filled with a dielectric material after depositing the first liner layer. The dielectric material and the first liner layer include substantially the same metal-contained ternary dielectric material. Excess portions of the dielectric material and the first liner layer over the top surface of the semiconductor substrate are removed.
    Type: Application
    Filed: August 2, 2018
    Publication date: April 4, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Yun PENG, Keng-Chu LIN
  • DEVICE AND METHOD OF DIELECTRIC LAYER
    Publication number: 20190103276
    Abstract: A method includes forming an interlayer dielectric (ILD) and a gate structure over a substrate. The gate structure is surrounded by the ILD. The gate structure is etched to form a recess. A first dielectric layer is deposited over sidewalls and a bottom of the recess and over a top surface of the ILD using a first Si-containing precursor. A second dielectric layer is deposited over and in contact with the first dielectric layer using a second Si-containing precursor different from the first Si-containing precursor. A third dielectric layer is deposited over and in contact with the second dielectric layer using the first Si-containing precursor. Portions of the first, second, and third dielectric layer over the top surface of the ILD are removed.
    Type: Application
    Filed: June 22, 2018
    Publication date: April 4, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Yun PENG, Chung-Chi KO, Keng-Chu LIN
  • DUMMY FIN STRUCTURES AND METHODS OF FORMING SAME
    Publication number: 20190103304
    Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.
    Type: Application
    Filed: August 16, 2018
    Publication date: April 4, 2019
    Inventors: Chin-Hsiang Lin, Keng-Chu Lin, Shwang-Ming Jeng, Teng-Chun Tsai, Tsu-Hsiu Perng, Fu-Ting Yen
  • Support structure for barrier layer of semiconductor device
    Patent number: 10181443
    Abstract: Among other things, one or more support structures and techniques for forming such support structures within semiconductor devices are provided. The support structure comprises an oxide infused silicon layer that is formed within a trench of a dielectric layer on a substrate of a semiconductor device. The oxide infused silicon layer results from a silicon layer that is exposed to oxide during an ultraviolet (UV) curing process. The oxide infused silicon layer is configured to support a barrier layer against a conductive structure formed on the barrier layer within the trench. In this way, the support structure provides pressure against the barrier layer so that the barrier layer substantially maintains contact with the conductive structure, to promote improved performance and reliability of the conductive structure.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: January 15, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Joung-Wei Liou, Keng-Chu Lin
  • Low-K dielectric layer and porogen
    Patent number: 10134632
    Abstract: A system and method for a low-k dielectric layer are provided. A preferred embodiment comprises forming a matrix and forming a porogen within the matrix. The porogen comprises an organic ring structure with fewer than fifteen carbons and a large percentage of single bonds. Additionally, the porogen may have a viscosity greater than 1.3 and a Reynolds numbers less than 0.5.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Joung-Wei Liou, Hui-Chun Yang, Yu-Yun Peng, Keng-Chu Lin
  • METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE WITH ETCH STOP LAYER
    Publication number: 20180166285
    Abstract: A method for forming a semiconductor device structure is provided. The method includes disposing a semiconductor substrate in a physical vapor deposition (PVD) chamber. The method also includes introducing a plasma-forming gas into the PVD chamber, and the plasma-forming gas contains an oxygen-containing gas. The method further includes applying a radio frequency (RF) power to a metal target in the PVD chamber to excite the plasma-forming gas to generate plasma. In addition, the method includes directing the plasma towards the metal target positioned in the PVD chamber such that an etch stop layer is formed over the semiconductor substrate.
    Type: Application
    Filed: October 12, 2017
    Publication date: June 14, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ya-Ling LEE, Shing-Chyang PAN, Keng-Chu LIN, Wen-Cheng YANG, Chih-Tsung LEE, Victor Y. LU
  • Semiconductor devices, methods of manufacture thereof, and inter-metal dielectric (IMD) structures
    Patent number: 9941214
    Abstract: Semiconductor devices, methods of manufacture thereof, and IMD structures are disclosed. In some embodiments, a semiconductor device includes an adhesion layer disposed over a workpiece. The adhesion layer has a dielectric constant of about 4.0 or less and includes a substantially homogeneous material. An insulating material layer is disposed over the adhesion layer. The insulating material layer has a dielectric constant of about 2.6 or less. The adhesion layer and the insulating material layer comprise an IMD structure.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: April 10, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yu-Yun Peng, Keng-Chu Lin, Joung-Wei Liou, Kuang-Yuan Hsu
  • Back-end-of-line (BEOL) interconnect structure
    Patent number: 9870944
    Abstract: A method of fabricating an interconnect structure on a wafer and an interconnect structure are provided. A dielectric layer is provided on the wafer, with the dielectric layer having a recess therein. A silicon (Si) layer is deposited in the recess. An interconnect is formed by providing a barrier layer and a conductive layer in the recess over the Si layer. The Si layer has a density that prevents or substantially prevents the barrier layer from moving away from the conductive layer and towards the dielectric layer during subsequent processing of the interconnect structure.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: January 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Joung-Wei Liou, Keng-Chu Lin
  • Semiconductor devices including conductive features with capping layers and methods of forming the same
    Patent number: 9812390
    Abstract: Semiconductor devices, methods of manufacture thereof, and methods of forming conductive features thereof are disclosed. A semiconductor device includes an insulating material layer disposed over a workpiece. The insulating material layer includes a silicon-containing material comprising about 13% or greater of carbon (C). A conductive feature is disposed within the insulating material layer. The conductive feature includes a capping layer disposed on a top surface thereof.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: November 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Chun Yang, Mei-Ling Chen, Keng-Chu Lin, Joung-Wei Liou
  • Flowable films and methods of forming flowable films
    Patent number: 9728402
    Abstract: An embodiment is a method including depositing a first flowable film over a substrate in a processing region, the first flowable film comprising silicon and nitrogen, curing the first flowable film in a first step at a first temperature with a first process gas and ultra-violet light, the first process gas including oxygen, curing the first flowable film in a second step at a second temperature with a second process gas and ultra-violet light, the second process gas being different than the first process gas, and annealing the cured first flowable film at a third temperature to convert the cured first flowable film into a silicon oxide film over the substrate.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: August 8, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Cheng Wang, Chun-Hao Hsu, Han-Ti Hsiaw, Keng-Chu Lin
  • Low-K Dielectric Layer and Porogen
    Publication number: 20170148676
    Abstract: A system and method for a low-k dielectric layer are provided. A preferred embodiment comprises forming a matrix and forming a porogen within the matrix. The porogen comprises an organic ring structure with fewer than fifteen carbons and a large percentage of single bonds. Additionally, the porogen may have a viscosity greater than 1.3 and a Reynolds numbers less than 0.5.
    Type: Application
    Filed: February 6, 2017
    Publication date: May 25, 2017
    Inventors: Joung-Wei Liou, Hui-Chun Yang, Yu-Yun Peng, Keng-Chu Lin
  • Surface passivation for germanium-based semiconductor structure
    Patent number: 9647090
    Abstract: The present disclosure provides a method forming a semiconductor device in accordance with some embodiments. The method includes receiving a substrate having a fin protruding through the substrate, wherein the fin is formed of a first semiconductor material, exposing the substrate in an environment including hydrogen radicals, thereby passivating the protruded fin using the hydrogen radicals, and epitaxially growing a cap layer of a second semiconductor material to cover the protruded fin.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: May 9, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Cheng Wang, Chien-Feng Lin, Jeng-Yang Pan, Keng-Chu Lin