Abstract: An output voltage Vout from a boost processing section 20 is divided by resistances 41 and 42, and a resultant divided output voltage Va is input to one of two input terminals of a comparator 45. A reference voltage Vb obtained by dividing a voltage Vcc by resistances 43 and 44 is input to the other input terminal of the comparator 45. The comparator 45 compares the divided output voltage Va with the reference voltage Vb, and when the divided output voltage Va is lower, outputs a HIGH voltage, and when the divided output voltage Va is higher, outputs a LOW voltage. Thereby, an signal oscillating section 10 performs oscillation at a radio frequency (an N-type CMOS FET 18 is in the OFF state) when the output voltage Vout does not exceed a threshold value determined by the reference voltage Vb, and performs oscillation at a low frequency (the N-type CMOS FET 18 is in the ON state) when the output voltage Vout exceeds the threshold value.

Abstract: One end of each of five resistors is connected to each of the two ends and the respective intermediate points of a cascade of four depression-type FETs, while the other ends of the five resistors are provided with a predetermined voltage. This configuration fixes the source-drain potential of the four FETs. This fixing of the source-drain potential of the FETs permits stable application of a bias voltage for turning ON the FETs between the gate and the source each FET, so as to ensure the ON-OFF switching of the FETs.

Abstract: A first low noise amplifier (LNA1 111) is provided with a control terminal (1115) for turning of/off the low noise amplifier (LNA1 111). Power terminals of the low noise amplifier (LNA1 111) and a second low noise amplifier (LNA2 112) are commonly connected, and are connected to a power supply (10) via a power supply switch (1114). Ground terminals of the two amplifiers (LNA1 111) and (LNA2 112) are commonly connected, and a constant current source (1 115) is connected between the common terminal and the ground. The amplifiers (LNA1 111) and (LNA2 112) are turned on/off by switching the voltage applied to the control terminal (1115) of the first low noise amplifier (LNA1 111) between a high potential and a low potential. The power supply switch (1114) is turned off during signal transmission. Therefore, an LNA block can be provided by using only one power supply switch (1114), whereby it is possible to reduce the number of devices from that in the prior art, thereby realizing a reduction in the size thereof.

Abstract: An object is to provide an antenna switch semiconductor integrated circuit which reduces a consumption current. To this end, of two control input signals which are fed to a logic circuit which controls turning on and off of a plurality of switching FETs, a control input signal for switching between a sending mode and a receiving mode is fed to an oscillation circuit, thereby making the oscillation circuit operate only during the sending mode under which the logic circuit needs a high voltage. A voltage raising circuit accordingly operates, whereby a raised voltage is supplied to the logic circuit. During the receiving mode, the oscillation circuit stops, and the voltage raising circuit stops. With a switch turned on using the logic circuit, a power source voltage is supplied directly to the logic circuit when the voltage raising circuit is not in operation. This shortens the operation time of the voltage raising circuit and reduces the consumption current.

Abstract: The present invention, which aims to provide a gallium arsenide field-effect transistor that can reduce degradation of field-effect transistor characteristics, and to realize miniaturization of the transistor, includes: a substrate; a mesa which includes a channel layer and is formed on the substrate; a source electrode formed on the mesa; a drain electrode; and a gate electrode, wherein, on the mesa, a top pattern is formed in which finger portions of the source electrode and the drain electrode which are formed in comb-shape are located so as to interdigitate, and a gate electrode is formed between the source electrode and the drain electrode, while common portions, which are base parts of the finger portions of the source and drain electrodes, are formed on the surface of the mesa, and the part located below the straight portion which is parallel to the finger portions of the gate electrode is electrically separated from the part located below a corner portion that connects neighboring straight portions of

Abstract: A diode logic circuit which can select a high voltage from among the voltages of a number of control voltage input terminals using a number of diodes made of Schottky junctions is integrally formed on a compound semiconductor substrate on which MESFET stages for switching and for securing isolations have been formed. In addition, the MESFET stages for switching are controlled by the voltages of the number of control voltage input terminals and the MESFET stages for securing isolations are controlled by the OR voltage that is outputted from the diode logic circuit.

Abstract: In a method of manufacturing a semiconductor device with a shallow trench isolation structure, trenches are formed to extend into a semiconductor substrate. Subsequently, a first insulating film is formed to fill the trenches and to cover a whole surface of the semiconductor substrate, and then a first chemical mechanical polishing (CMP) method is carried out to remove the first insulating film such that the first insulating film is left only in the trenches. Subsequently, a second insulating film is formed to fill the trenches and to cover a whole surface of the semiconductor substrate, and a second CMP method is carried out to remove the second insulating film such that the second insulating film is left only in the trenches.

Abstract: The present invention aims to provide a miniaturized semiconductor device at low-cost having high integration density and for restraining an increase of an insertion loss and a deterioration of an isolation characteristic of a circuit resulting from parasitic inductance of gold wires, the semiconductor device comprising a control semiconductor chip 110, a switch circuit semiconductor chip 111, a substrate 410, external terminals 113, gold wires 210 and MIM capacitors 120 and 430, the control semiconductor chip 110 controlling a high frequency signal processing by the switch circuit semiconductor chip 111, the switch circuit semiconductor chip 111 being mounted on the control semiconductor chip 110 and processing the high frequency signal, the substrate 410 being on which the control semiconductor chip 110 is mounted, the external terminals 113 being interfaces with outside, the gold wires 210 connecting among the control semiconductor chip 110, the switch circuit semiconductor chip 111 and the external termin

Abstract: An object is to provide an antenna switch semiconductor integrated circuit which reduces a consumption current. To this end, of two control input signals which are fed to a logic circuit which controls turning on and off of a plurality of switching FETs, a control input signal for switching between a sending mode and a receiving mode is fed to an oscillation circuit, thereby making the oscillation circuit operate only during the sending mode under which the logic circuit needs a high voltage. A voltage raising circuit accordingly operates, whereby a raised voltage is supplied to the logic circuit. During the receiving mode, the oscillation circuit stops, and the voltage raising circuit stops. With a switch turned on using the logic circuit, a power source voltage is supplied directly to the logic circuit when the voltage raising circuit is not in operation. This shortens the operation time of the voltage raising circuit and reduces the consumption current.

Abstract: One end of each of five resistors is connected to each of the two ends and the respective intermediate points of a cascade of four depression-type FETs, while the other ends of the five resistors are provided with a predetermined voltage. This configuration fixes the source-drain potential of the four FETs. This fixing of the source-drain potential of the FETs permits stable application of a bias voltage for turning ON the FETs between the gate and the source each FET, so as to ensure the ON-OFF switching of the FETs.

Abstract: The invention is directed to the provision of a two-input, four-output high frequency switch circuit that can prevent the occurrence of in-band ripples of insertion loss in an ON path. The high frequency switch circuit is constructed from six field effect transistors, and a signal is passed through a selected one of signal paths in the two-input, four-output high frequency signal switch having a total of six signal terminals, wherein four additional field effect transistors, each of which, when ON, provides a characteristic impedance matched to the characteristic impedance of an external circuit, are respectively connected between ground and the signal paths leading to the remaining four signal terminals to which the signal is not passed and which therefore become open ends.

Abstract: The invention is directed to the provision of a two-input, four-output high frequency switch circuit that can prevent the occurrence of in-band ripples of insertion loss in an ON path. The high frequency switch circuit is constructed from six field effect transistors, and a signal is passed through a selected one of signal paths in the two-input, four-output high frequency signal switch having a total of six signal terminals, wherein four additional field effect transistors, each of which, when ON, provides a characteristic impedance matched to the characteristic impedance of an external circuit, are respectively connected between ground and the signal paths leading to the remaining four signal terminals to which the signal is not passed and which therefore become open ends.