Abstract: The present invention provides a combination product which comprises: (1) a polyaldehyde obtained by introducing an aldehyde group into a branched glucose in a ?-1,3-glucan, and (2) a polyamine obtained by increasing the molecular weight of a poly-L-lysine. The combination product according to the present invention is useful as a material for a tissue adhesive hydrogel which can be used as a hemostatic agent or the like which exhibits low risks for viral infections and the like, high biodegradability and biocompatibility, excellent safety, a good adhesion rate and a good adhesion strength.

Abstract: A paste in which semiconductor fine grain such as titanium oxide fine grain or the like and a binder made of a polymer compound are mixed is coated onto a transparent conductive substrate and sintered, thereby forming a semiconductor layer made of the semiconductor fine grain, after that, ultraviolet rays are irradiated to the semiconductor layer and, by using a photocatalyst effect of the semiconductor fine grain, an organic substance remaining in the semiconductor layer is removed.

Abstract: A paste in which semiconductor fine grain such as titanium oxide fine grain or the like and a binder made of a polymer compound are mixed is coated onto a transparent conductive substrate and sintered, thereby forming a semiconductor layer made of the semiconductor fine grain, after that, ultraviolet rays are irradiated to the semiconductor layer and, by using a photocatalyst effect of the semiconductor fine grain, an organic substance remaining in the semiconductor layer is removed.

Abstract: A paste in which semiconductor fine grain such as titanium oxide fine grain or the like and a binder made of a polymer compound are mixed is coated onto a transparent conductive substrate and sintered, thereby forming a semiconductor layer made of the semiconductor fine grain, after that, ultraviolet rays are irradiated to the semiconductor layer and, by using a photocatalyst effect of the semiconductor fine grain, an organic substance remaining in the semiconductor layer is removed.

Abstract: In a dye-sensitized photoelectric transfer device having a semiconductor layer and an electrolyte layer between a transparent conductive substrate and a counter conductive substrate, the semiconductor layer is composed of titania nanotubes, and a sensitizing dye is retained by the titania nanotubes. The titania nanotubes preferably have an anatase-type crystalline form. The dye-sensitized photoelectric transfer device is used as a dye-sensitized solar cell.

Abstract: It is an object of the present invention to provide a protein having a drug transport activity, a method for screening a compound that promotes or inhibits the activity of the drug transporter, a compound obtained by the method, an antibody against the drug transporter, a pharmaceutical composition comprising the same, or the like. The protein with a drug transport activity of the present invention has an amino acid sequence represented by SEQ ID NO: 1.

Abstract: A fast transfer bus system capable of fast data transfer with no reflection at branch points. Four LSIs having constant-impedance interfaces are connected via two variable resistors each having three signal terminals. A variable impedance LSI is connected between these variable resistors. When the LSIs connected to the variable resistor do not work as a bus driver, three variable resistance elements in each variable resistor are set to have a value of ⅓ of the characteristic impedance Zo of connection lines, and are connected in a Y-letter shape. When one of LSIs connected to the variable resistor works as a bus driver, the values of the variable resistance elements are set to low impedance or Zo.

Abstract: No matter how large or small a data capacity in an address space is, code efficiency and data processing performance are improved without deteriorating the usage comfort of a CPU. Since a data processor is configured employing an instruction control unit (CONT) capable of changing interpretation of identical instructions according to dynamic switching of operation modes, dynamic switching can be made between the operation mode that limits data areas in an address space to give higher priority to higher code efficiency and quicker instruction fetch, and the operation mode that eliminates limitations on usable data areas to the fullest extent possible. Thereby, the advantages of instructions of contracted form and the like can be offered without deteriorating the usage comfort of the CPU.

Abstract: Apparatus for interconnecting logic boards is provided with a backplane, a plurality of logic boards connected to the backplane, and a plurality of interconnecting boards, connected to the backplane, for interconnecting the plurality of logic boards. In the apparatus, the plurality of logic boards are connected to the backplane with the logic boards in vertical position at right angles with the interconnecting boards and a specified distance away from the interconnecting boards.

Abstract: Apparatus for interconnecting logic boards is provided with a backplane, a plurality of logic boards connected to the backplane, and a plurality of interconnecting boards, connected to the backplane, for interconnecting the plurality of logic boards. In the apparatus, the plurality of logic boards are connected to the backplane with the logic boards in vertical position at right angles with the interconnecting boards and a specified distance away from the interconnecting boards.

Abstract: A semiconductor integrated circuit system having a function of automatically adjusting an output resistance value with reference to a temperature of an LSI which is operating. When a count value obtained from a counter by counting the output of a timer becomes equal to a predetermined value, a temperature sensor measures temperatures of LSIs. If a temperature fluctuation measured from a previous measured value is greater than a predetermined width, then a control apparatus issues an output resistance value adjustment request signal to output resistance adjustment units of the LSIs.

Abstract: In a simultaneous bidirectional transmission circuit for conducting simultaneous two-way communication between LSIs via a transmission line, an input/output circuit connected to the transmission line is included in an LSI. The input/output circuit has a driver and a receiver. The driver sends out an output signal depending on a logical signal within the LSI to the transmission line. The receiver receives a mixed signal having a mixture of a received signal and the output signal via the transmission line. The signal to be received by the receiver in an LSI has been sent out to the transmission line by the other party i.e., another LSI in communication therewith. The receiver receives the logical signal output as well. The receives derives a difference between the mixed signal and the logical signal output, thereby removing the component of the logical signal from the mixed signal, and outputs the received signal.

Abstract: Data is transmitted from any one of a plurality of transmitters in synchronism with a first clock. A receiver receives the data in synchronism with the first clock and a second clock having a predetermined phase relationship with the first clock. Control information is previously held in the receiver regarding data reception conditions associated with the plurality of transmitters to control reception conditions of the receiver on the basis of the control information.

Abstract: A first variable delay circuit delays the reception data from the transmitting unit which is outputted from an input buffer and generates the delayed data to a data unidentifying time detecting portion. First and second latches have latch timings at regular intervals before and after a latch timing of a third latch for receiving and outputting by second and third variable delay circuits, respectively. In an adjusting operation, delay amounts of the second and third variable delay circuits are fixed to a value which is sufficiently smaller than a transfer period, a delay amount of the variable delay circuit is increased, a judging circuit detects a preceding edge of the reception data, subsequently, the delay amounts of the second and third variable delay circuits are sequentially increased while maintaining to the same value, and a following edge of the reception data is detected. In this instance, the timing of the third latch is set to the optimum point of the maximum margin.

Abstract: A semiconductor integrated circuit comprising a clock pulse generator, peripheral function blocks and bus master modules. The peripheral function blocks are commonly supplied with a first system clock signal of a constant frequency generated on the basis of the output from the clock pulse generator. The bus master modules are fed with a second system clock signal generated on the basis of the pulse generator output. The frequency of the second system clock signal is variable and lower than that of the first system clock signal. The function blocks supplied with the first system clock signal are connected to a data bus separate from the one connected to the function blocks fed with the second system clock signal.

Abstract: A simultaneous bidirectional transmission apparatus for transmitting and receiving differential signals solves a generation of pulse noise problem in the receiving circuit due to the inversion of the output of the transmission circuit. For a pair of input/output devices connected together by transmission lines, each input/output device has a differential transmitting circuit, a differential receiving circuit and six resistors. The output of the transmitting circuit does not affect an input to the receiving circuit, and the receiving circuit receives only the output of the transmitting circuit of the other input/output device. The resistors, a passive element circuit and the output resistance of the transmitting circuit form, in combination, a waveform shaping filter and a matching terminating circuit.

Abstract: A data transfer apparatus includes a transmitting apparatus having a pulse generation circuit for generating a plurality of data and a clock having a predetermined timing relation to the plurality of data, a receiving apparatus having latch circuits supplied with the clock and data for latching the plurality of data at a timing of the clock, respectively, transmission lines for connecting the transmitting apparatus and the receiving apparatus, a variable delay circuit for delaying the clock or data to be supplied to the latch circuits, and a variable delay control circuit for controlling an amount of delay of the variable delay circuit by means of output signals of the latch circuits to thereby minimize the cycle time of the data and clock in the data transfer between apparatuses.

Abstract: A method of controlling a cache memory disposed between a CPU and a main memory, wherein pairs of data and an address to be written in the cache memory are stored into a buffer memory. A plurality of pairs of data and an address read from the buffer memory are processed to compare the address fields thereof. Based on results of the comparisons, there is determined a write control for writing the data in the cache memory which has been subdivided into a plurality of banks. As a result, the plural pairs of data and an address are written into the plural banks of the cache memory, the addresses of the respective pairs being different from each other. With the provisions set forth above, the write operation can be independently conducted for each bank of the cache memory, thereby improving the write throughput.

Abstract: On-resistance is minimized in a high-current integrated circuit by efficient use of wiring spaces for various layers in a wiring construction with multilayer-wiring connections between transistor electrode regions and electrode terminals. The construction utilizes multiple wiring layers and interlayer insulation films between the wiring layers, which insulation films have connecting holes at specified portions of the wiring structure. By incorporating connecting holes at select locations, and utilizing spaces which are not used for connecting holes as spaces for routing different wiring layers, the wiring structure allows overlapping wiring connections between the transistor electrode regions and the electrode terminals.

Abstract: Operation of a clock generating circuit is stopped when the oscillation signals to be selectively transmitted to the clock generating circuit via a multiplexer are switched. The oscillation signals are generated by a first oscillation circuit at a relatively high frequency and by a second oscillation circuit which steadily oscillates at a relatively low frequency. The clock generating operation is resumed in synchronization with the switched oscillation signals.