Abstract: A semiconductor integrated circuit device is provided which include a plurality of cell columns each having a number of unit cells previously fabricated on a semiconductor substrate selected from the plural kinds of unit cells which are formed in desired circuits by electrically connecting circuit devices previously arranged. Each column includes at least one kind of unit cell of a dynamic circuit which has a node in a floating state during the operation of the cell unit. A fixed potential shield layer is also provided on the cell columns so as to cover the nodes of the dynamic circuits. By virtue of this, a wiring area for electrically connecting the desired cell units can be located between the cell columns and above the shield layer. In other words, signal wirings in the wiring area can pass over the nodes of the dynamic circuits. without adverse parasitic effects. The unit cell can also be provided with a precharge circuit comprising a standard cell and an in-cell wiring layer.

Abstract: An information processing system includes a plurality of functional blocks (neurons) and a data bus for transmitting in common the outputs of the individual functional blocks (neurons). Data transaction among the functional blocks (neurons) is performed through the data bus on the time-division basis. For preventing the outputs from conflicting or competition, addresses are assigned to the individual blocks (neurons), respectively, so that only the functional blocks (neuron) having the own address designated by the address signal supplied through an address bus outputs data signal onto the data bus, while the other functional blocks (neurons) receive the information on the data bus as the signal originating in the functional block whose address is designated at that time point. The addresses are sequentially changed. During a round of the address signals, data are transmitted from given functional blocks (neurons) to other given functional blocks (neurons).

Abstract: This invention discloses a clock distribution system which distributes a first clock signal as a reference clock as the reference for the phase and frequency to each processing unit (e.g. LSI) and generates a multi-phase second clock signal to be used in each processing unit by a delay circuit group whose delay time is adjusted.

Abstract: A dynamic semiconductor logic circuit comprising a MOS FET logic section for effecting a high-speed logic operation in response to input logic signals after precharging of an output mode and internal nodes the logic section, a CMOS/BiCMOS output buffer section for outputting a result of the logic operation, and a noise suppression section for preventing erroneous operations without sacrificing the high-speed operation characteristic. The circuit, which is fabricated with 0.5-.mu.m-rule technology and operates at high speed with a low-voltage power source of 4.5 V or less, has a precharging section for precharging the output node and internal nodes of the MOS FET logic section and a noise suppression section for latching the output node of the logic section to the source potential by feeding back the output of an output buffer section in order to enlarge the soft error margin. The latching current is held at less than a predetermined ratio to maintain the high-speed operation characteristic.

Abstract: A semiconductor integrated circuit device is provided which includes a logic circuit utilizing an error detection code.

Abstract: An output signal of a logic portion is inputted to the gate of FET inside an output buffer portion to inverse the signal polarity by this FET and is outputted through a bipolar transistor effecting an emitter follower operation or the like. An FET controlled by a clock signal is disposed between the base of the bipolar transistor and the ground and an FET which is turned ON during a pre-charge operation and when the bipolar transistor is OFF during logic calculation is disposed between the emitter and the ground so as to short-circuit the emitter and the ground during the pre-charge operation. In this manner, higher operation speed, higher integration density and high operation margin can be accomplished without losing the characteristic features of a Bi-CMOS dynamic logic circuit in its high operation speed and low power dissipation.

Abstract: An output interface circuit comprises a CMOS circuit including a pair of complementary MOS transistors and receiving an input signal at the gates of the paired MOS transistors, a bipolar transistor having its base connected to the output of the CMOS circuit and its emitter from which an output signal is delivered, and a control circuit connected between the paired MOS transistors and operable, upon the fall of the output signal, to cut off a current flowing through any one of the paired MOS transistors so as to control the low level at the output of the CMOS circuit such that the low level does not fall before a potential level by which the low level of the output signal is permitted to be at a desirable predetermined potential level. Specifically, the CMOS circuit includes a pair of complementary MOS transistors comprised of a P-type MOS transistor and an N-type MOS transistor and receives an input signal of CMOS level to operate in inverter fashion.

Abstract: A laminated multilayer electric circuit is comprised of wafers having each internal electric circuits and laminated one after another. A signal transfer circuit used in the laminated multilayer electric circuit for transfer of signals between the wafers through an electrostatic capacitor has a receiving circuit of sufficiently high input resistance for receiving a signal from a capacitance electrode forming the electrostatic capacitor, and a circuit for clamping the level of the signal substantially within the input amplitude for the receiving circuit. The signal transfer circuit permits the signal transfer to be performed not through a flip-flop or the like and consequently at high speeds.

Abstract: An output circuit comprises an output transistor circuit for applying an output signal to a transmission line connected to an output terminal, a circuit for driving the output transistor circuit in response to an input signal applied to an input terminal, and a control circuit by which the signal amplitude of a first wave applicable to the transmission line with a load connected to the output terminal through the transmission line is rendered approximately one half of the output signal amplitude with a load directly connected to the output terminal. The control circuit includes a monitoring transistor within the same chip as the output transistor circuit, a selected one of the output resistance and input signal of the output transistor circuit being controlled in accordance with the magnitude of the drain current of the monitoring transistor to adjust the amplitude of the signal applied to the transmission line.

Abstract: A novel and efficient method is proposed for the preparation of isosorbide-5-nitrate which is a promising medicinal compound for several diseases due to disorder in heart. The method comprises direct nitration of isosorbide with a concentrated nitric acid in a specific reaction medium containing an aromatic hydrocarbon solvent, e.g. benzene, in addition to conventional acetic acid and acetic anhydride. After neutralization of the reaction mixture and removal of the dinitrate as a byproduct therefrom, the reaction mixture is admixed with an aqueous solution of sodium hydroxide so that a sodium salt of isosorbide-5-nitrate is precipitated in the form of a hydrate, which is a novel compound not known in the prior art. This hydrate sodium salt is then decomposed with an acid to give the desired isosorbide-5-nitrate in a high yield.

Abstract: A novel and very elegant method is proposed for the preparation of N.sub.1 -(2-tetrahydrofuryl)-5-substituted or -unsubstituted uracil, especially, N.sub.1 -(2-tetrahydrofuryl)-5-fluorouracil, by the reaction of the corresponding 5-substituted uracil compound with 2,3-dihydrofuran. The reaction is performed in the presence of a chlorosilane compound, e.g. dimethyldichlorosilane, and a catalytic amount of an organic amine compound and can proceed very rapidly without disadvantageous side reactions to give the objective compound with high purity in a high yield.