Patents by Inventor Kenichi Matsushita

Kenichi Matsushita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240322518
    Abstract: Provided is a laser irradiation device including: a laser light source that emits laser light; and a control unit that performs control relating to irradiation of a substrate with laser light. The control unit acquires operation parameters including a detection value from a detection unit provided in the laser irradiation device, derives predicted quality information by inputting the acquired operation parameters to a learning model that outputs predicted quality information of a product including the substrate irradiated with the laser light in a case where the operation parameters are input, and outputs the derived predicted quality information and the acquired operation parameters in association with each other.
    Type: Application
    Filed: March 22, 2022
    Publication date: September 26, 2024
    Inventors: Kenichi Ohmori, Yuzaburo Ohta, Rei Matsushita
  • Patent number: 12087850
    Abstract: This semiconductor device includes: a semiconductor layer having a first face and a second face, the semiconductor layer including a first trench and a second trench in a first face side; a first gate electrode in the first trench; a first conductive layer in the first trench and between the first gate electrode and the second face, the first conductive layer being electrically separated from the first gate electrode; a second gate electrode in the second trench; a second conductive layer in the second trench and between the second gate electrode and the second face; a first electrode on a the first face side; a second electrode on a side of the second face; a first gate electrode pad being electrically connected to the first gate electrode; and a second gate electrode pad being electrically connected to the second gate electrode.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: September 10, 2024
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Norio Yasuhara, Yoko Iwakaji, Yusuke Kawaguchi, Daiki Yoshikawa, Kenichi Matsushita, Shoko Hanagata, Tomoko Matsudai, Hiroko Itokazu, Keiko Kawamura
  • Publication number: 20240283058
    Abstract: A fuel cell system includes a microprocessor configured to perform, during an external power supply in which power is supplied to an external load, controlling a power generation of a fuel cell so as to generate a power at a predetermined power generation efficiency and supplying a surplus power not consumed out of the generated power of the fuel cell to a battery to charge the battery. The controlling includes, during the external power supply, stopping the power generation of the fuel cell when a charge rate of the battery becomes a first predetermined value or larger, controlling an output of the battery so that the power of the battery is supplied to the external load, and resuming the power generation of the fuel cell when the charge rate becomes a second predetermined value smaller than the first predetermined value or lower.
    Type: Application
    Filed: February 13, 2024
    Publication date: August 22, 2024
    Inventors: Seiji Takaya, Masanori Matsushita, Morio Kayano, Kenichi Shimizu, Kenta Suzuki, Suguru Yamanaka, Satoshi Oshima, Takaharu Watanabe
  • Patent number: 11798997
    Abstract: A semiconductor device includes: cell and termination regions; a first electrode; a semiconductor part on the first electrode; an insulating film on the semiconductor part in the termination region; mutually-separated second electrodes on the insulating film arranged in a direction from a center toward an outer perimeter of the semiconductor part when viewed from above; a first floating electrode in the insulating film overlapping a gap between an adjacent pair of the second electrodes when viewed from above, and facing one of the pair via the insulating film; and a second floating electrode in the insulating film and separated from and overlapping the first floating electrode in the gap when viewed from above, and facing the other of the pair of second electrodes via the insulating film, wherein the overlapping portion of the second floating electrode is positioned below a portion of the first floating electrode overlapping the gap.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: October 24, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Kenichi Matsushita, Norio Yasuhara
  • Publication number: 20230307443
    Abstract: A semiconductor device includes a first electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, a second electrode, a conductive part, and a fourth semiconductor region. The first semiconductor region is located above the first electrode. The second semiconductor region is located on the first semiconductor region. The third semiconductor region is located on the second semiconductor region. The second electrode is located on the second and third semiconductor regions. The second electrode is electrically connected with the second and third semiconductor regions. The conductive part includes a first conductive region and a second conductive region. The first conductive region faces the first to third semiconductor regions via an insulating film. The second conductive region is located around the second electrode. The fourth semiconductor region is located around the second semiconductor region.
    Type: Application
    Filed: September 2, 2022
    Publication date: September 28, 2023
    Inventor: Kenichi MATSUSHITA
  • Publication number: 20230085921
    Abstract: A semiconductor device includes a semiconductor part and first to fourth electrodes. The semiconductor part includes a first layer of a first conductivity type and second and third layers of a second conductivity type. The first and second electrodes are provided on back and front surfaces of the semiconductor part, respectively. The third electrode is provided inside a trench of the semiconductor part. The fourth electrode is provided on the front surface of the semiconductor part. The first layer extends between the first electrode and the second and fourth electrodes. The second layer is provided between the first layer and the second electrode. The third layer is provided between the first layer and the fourth electrode. The third electrode includes an end provided between the third layer and the fourth electrode. The third layer is electrically connected to the second electrode via the third and fourth electrodes.
    Type: Application
    Filed: March 8, 2022
    Publication date: March 23, 2023
    Inventor: Kenichi MATSUSHITA
  • Publication number: 20230090328
    Abstract: A semiconductor device includes: a first semiconductor layer located in a diode region, the first semiconductor layer including a plurality of first semiconductor regions and a plurality of second semiconductor regions alternately arranged in a first direction; a second semiconductor layer located in the IGBT region; and a third semiconductor layer located on the first semiconductor layer in the diode region, an impurity concentration of the third semiconductor layer having a maximum at a first position in a second direction, an impurity concentration of the first semiconductor region having a maximum at a second position in the second direction, a third position being separated from the upper surface of the first electrode by a length that is 3 times a distance between the second position and a lower end of the third semiconductor layer, the first position being the same as or lower than the third position.
    Type: Application
    Filed: March 8, 2022
    Publication date: March 23, 2023
    Inventors: Kenichi MATSUSHITA, Mitsuhiko KITAGAWA
  • Publication number: 20220302265
    Abstract: A semiconductor device includes: cell and termination regions; a first electrode; a semiconductor part on the first electrode; an insulating film on the semiconductor part in the termination region; mutually-separated second electrodes on the insulating film arranged in a direction from a center toward an outer perimeter of the semiconductor part when viewed from above; a first floating electrode in the insulating film overlapping a gap between an adjacent pair of the second electrodes when viewed from above, and facing one of the pair via the insulating film; and a second floating electrode in the insulating film and separated from and overlapping the first floating electrode in the gap when viewed from above, and facing the other of the pair of second electrodes via the insulating film, wherein the overlapping portion of the second floating electrode is positioned below a portion of the first floating electrode overlapping the gap.
    Type: Application
    Filed: September 10, 2021
    Publication date: September 22, 2022
    Inventors: Kenichi MATSUSHITA, Norio YASUHARA
  • Publication number: 20220302288
    Abstract: This semiconductor device includes: a semiconductor layer having a first face and a second face, the semiconductor layer including a first trench and a second trench in a first face side; a first gate electrode in the first trench; a first conductive layer in the first trench and between the first gate electrode and the second face, the first conductive layer being electrically separated from the first gate electrode; a second gate electrode in the second trench; a second conductive layer in the second trench and between the second gate electrode and the second face; a first electrode on a the first face side; a second electrode on a side of the second face; a first gate electrode pad being electrically connected to the first gate electrode; and a second gate electrode pad being electrically connected to the second gate electrode.
    Type: Application
    Filed: September 13, 2021
    Publication date: September 22, 2022
    Inventors: Norio YASUHARA, Yoko IWAKAJI, Yusuke KAWAGUCHI, Daiki YOSHIKAWA, Kenichi MATSUSHITA, Shoko HANAGATA, Tomoko MATSUDAI, Hiroko ITOKAZU, Keiko KAWAMURA
  • Patent number: 11335769
    Abstract: A semiconductor device includes a semiconductor part, a terminal insulating film, a first protective film, a second electrode, a terminal electrode, a first insulating film, and a second protective film. The terminal insulating film is provided on the semiconductor part in the terminal region. The first protective film is provided on the terminal insulating film. The first and second protective films includes silicon and nitrogen. The second electrode is provided on the semiconductor part in the cell region and includes an end portion located on the first protective film. The terminal electrode is provided on the first protective film in the terminal region and is connected to the semiconductor part. The first insulating film is provided on the first protective film. The first insulating film includes hydrogen and contacts the second electrode and the terminal electrode. The second protective film covers the first insulating film.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: May 17, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Kenichi Matsushita, Tatsuya Ohguro
  • Patent number: 11322581
    Abstract: According to one embodiment, a semiconductor device includes first, second, and third electrodes, first and fourth semiconductor regions of a first conductivity type, and second and third semiconductor regions of a second conductivity type. The third semiconductor region is provided around the second semiconductor region along a first plane crossing a first direction from the first electrode toward the first semiconductor region and is separated from the second semiconductor region. The fourth semiconductor region is provided around the third semiconductor region along the first plane, and has a greater impurity concentration of the first conductivity type than the first semiconductor region. The second electrode is provided on the second semiconductor region and is electrically connected to the second semiconductor region.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: May 3, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Kenichi Matsushita
  • Publication number: 20220085154
    Abstract: A semiconductor device includes a semiconductor part, a terminal insulating film, a first protective film, a second electrode, a terminal electrode, a first insulating film, and a second protective film. The terminal insulating film is provided on the semiconductor part in the terminal region. The first protective film is provided on the terminal insulating film. The first and second protective films includes silicon and nitrogen. The second electrode is provided on the semiconductor part in the cell region and includes an end portion located on the first protective film. The terminal electrode is provided on the first protective film in the terminal region and is connected to the semiconductor part. The first insulating film is provided on the first protective film. The first insulating film includes hydrogen and contacts the second electrode and the terminal electrode. The second protective film covers the first insulating film.
    Type: Application
    Filed: February 9, 2021
    Publication date: March 17, 2022
    Inventors: Kenichi Matsushita, Tatsuya Ohguro
  • Publication number: 20210280671
    Abstract: According to one embodiment, a semiconductor device includes first, second, and third electrodes, first and fourth semiconductor regions of a first conductivity type, and second and third semiconductor regions of a second conductivity type. The third semiconductor region is provided around the second semiconductor region along a first plane crossing a first direction from the first electrode toward the first semiconductor region and is separated from the second semiconductor region. The fourth semiconductor region is provided around the third semiconductor region along the first plane, and has a greater impurity concentration of the first conductivity type than the first semiconductor region. The second electrode is provided on the second semiconductor region and is electrically connected to the second semiconductor region.
    Type: Application
    Filed: September 9, 2020
    Publication date: September 9, 2021
    Inventor: Kenichi Matsushita
  • Patent number: 11114526
    Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type. The semiconductor substrate includes a first semiconductor region of a second conductivity type at a surface thereof, a second semiconductor region of the second conductivity type at the surface and surrounding the first semiconductor region, a third semiconductor region of the second conductivity type provided in the second semiconductor region at the surface and surrounding the first semiconductor region. The third semiconductor region has a concentration of a second conductivity type impurity higher than that of the second semiconductor region. A first insulating film is provided on a part of the first surface at which the second semiconductor region is provided. the first insulating film having an opening that exposes. A first electrode is provided on the first insulating film and electrically connected to the third semiconductor region via the opening.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: September 7, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Kenichi Matsushita
  • Patent number: 11088789
    Abstract: According to one embodiment, a signal quality monitoring apparatus includes a signal processor, a comparator and a determiner. The processor obtains output signals from a first transmitter and a second transmitter which are mutually redundant and respectively reproduce digital broadcast signals based on a common origin signal, and generates a first signal based on the output signal from the first transmitter and a second signal based on the output signal from the second transmitter. The comparator compares the first signal and the second signal. The determiner determines a quality of the digital broadcast signal based on a result of the comparison.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: August 10, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, Toshiba Infrastructure Systems & Solutions Corporation
    Inventors: Kenichi Matsushita, Mikihiko Iwaida, Noboru Taga, Hideki Ono
  • Patent number: 10957773
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, a first ring-shaped region, a second ring-shaped region, a second electrode, a third electrode, a first conductive layer, and a semi-insulating layer. The first ring-shaped region surrounds the second semiconductor region, and is provided between the second and third semiconductor regions. The second ring-shaped region surrounds the first ring-shaped region, and is provided between the first ring-shaped region and the third semiconductor region. The first conductive layer surrounds the second electrode, and is provided on the first ring-shaped region, the second ring-shaped region, and a first region of the first semiconductor region with an insulating layer interposed. The first region is positioned between the first and second ring-shaped regions.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: March 23, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Kenichi Matsushita
  • Publication number: 20210074824
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, a first ring-shaped region, a second ring-shaped region, a second electrode, a third electrode, a first conductive layer, and a semi-insulating layer. The first ring-shaped region surrounds the second semiconductor region, and is provided between the second and third semiconductor regions. The second ring-shaped region surrounds the first ring-shaped region, and is provided between the first ring-shaped region and the third semiconductor region. The first conductive layer surrounds the second electrode, and is provided on the first ring-shaped region, the second ring-shaped region, and a first region of the first semiconductor region with an insulating layer interposed. The first region is positioned between the first and second ring-shaped regions.
    Type: Application
    Filed: February 7, 2020
    Publication date: March 11, 2021
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Kenichi MATSUSHITA
  • Patent number: 10811406
    Abstract: A semiconductor device has a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a first conductive layer disposed on a main surface of the first semiconductor region, and a second conductive layer disposed on a main surface of the second semiconductor region. The first conductive layer has a first diffusion layer of the first conductivity type, a plurality of second diffusion layers of the first conductivity type, the second diffusion layers having higher impurity concentration than the first diffusion layer, and a plurality of third diffusion layers of the first conductivity type that are included in the first semiconductor region, or are arranged apart from one another to contact the first and second semiconductor regions, the third diffusion layers being arranged apart from the plurality of second diffusion layers and having higher impurity concentration than the first diffusion layer.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: October 20, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Kenichi Matsushita
  • Publication number: 20200235093
    Abstract: A semiconductor device has a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a first conductive layer disposed on a main surface of the first semiconductor region, and a second conductive layer disposed on a main surface of the second semiconductor region. The first conductive layer has a first diffusion layer of the first conductivity type, a plurality of second diffusion layers of the first conductivity type, the second diffusion layers having higher impurity concentration than the first diffusion layer, and a plurality of third diffusion layers of the first conductivity type that are included in the first semiconductor region, or are arranged apart from one another to contact the first and second semiconductor regions, the third diffusion layers being arranged apart from the plurality of second diffusion layers and having higher impurity concentration than the first diffusion layer.
    Type: Application
    Filed: April 9, 2020
    Publication date: July 23, 2020
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Kenichi MATSUSHITA
  • Publication number: 20200153568
    Abstract: According to one embodiment, a signal quality monitoring apparatus includes a signal processor, a comparator and a determiner. The processor obtains output signals from a first transmitter and a second transmitter which are mutually redundant and respectively reproduce digital broadcast signals based on a common origin signal, and generates a first signal based on the output signal from the first transmitter and a second signal based on the output signal from the second transmitter. The comparator compares the first signal and the second signal. The determiner determines a quality of the digital broadcast signal based on a result of the comparison.
    Type: Application
    Filed: November 13, 2019
    Publication date: May 14, 2020
    Applicants: KABUSHIKI KAISHA TOSHIBA, Toshiba Infrastructure Systems & Solutions Corporation
    Inventors: Kenichi MATSUSHITA, Mikihiko IWAIDA, Noboru TAGA, Hideki ONO