Abstract: A semiconductor device according to an embodiment includes a semiconductor layer having a first and a second plane; emitter and collector electrode; a trench gate electrode extending in a first direction substantially parallel to the first plane; a dummy trench gate electrode extending in the first direction; a p base region; an emitter region; an n base region; a collector region; a trench gate insulating film; a dummy trench gate electrode; a dummy trench gate insulating film; a first gate pad electrode connected to the trench gate electrode and the dummy trench gate electrode; a first electric resistor connected between the first gate pad electrode and the trench gate electrode, and a second electric resistor connected between the first gate pad electrode and the dummy trench gate electrode. A CR time constant of the trench gate electrode is less than a CR time constant of the dummy trench gate electrode.

Abstract: A semiconductor device has a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a first conductive layer disposed on a main surface of the first semiconductor region, and a second conductive layer disposed on a main surface of the second semiconductor region. The first conductive layer has a first diffusion layer of the first conductivity type, a plurality of second diffusion layers of the first conductivity type, the second diffusion layers having higher impurity concentration than the first diffusion layer, and a plurality of third diffusion layers of the first conductivity type that are included in the first semiconductor region, or are arranged apart from one another to contact the first and second semiconductor regions, the third diffusion layers being arranged apart from the plurality of second diffusion layers and having higher impurity concentration than the first diffusion layer.

Abstract: A semiconductor device according to an embodiment includes a semiconductor layer having a first and a second plane; emitter and collector electrode; a trench gate electrode extending in a first direction substantially parallel to the first plane; a dummy trench gate electrode extending in the first direction; a p base region; an emitter region; an n base region; a collector region; a trench gate insulating film; a dummy trench gate electrode; a dummy trench gate insulating film; a first gate pad electrode connected to the trench gate electrode and the dummy trench gate electrode; a first electric resistor connected between the first gate pad electrode and the trench gate electrode, and a second electric resistor connected between the first gate pad electrode and the dummy trench gate electrode. A CR time constant of the trench gate electrode is less than a CR time constant of the dummy trench gate electrode.

Abstract: According to one embodiment, a transmission device includes an insertion unit, an allocation unit, a division unit, an IFFT unit, a phase rotation unit, and a transmission unit. The phase rotation unit performs a phase rotation to reduce a PAPR characteristic for each block on which inverse fast Fourier transform has been performed. The transmission unit combines transmission signals, on each of which a phase rotation has been performed by the phase rotation unit, and transmits the combined transmission signal to an external device. In addition, the division unit includes a predetermined band and at least one pilot symbol located outside another of end of this predetermined band on an opposite side of the one end into one block.

Abstract: A semiconductor device comprising: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided on the first semiconductor region; an insulating portion provided on the first semiconductor region; a third semiconductor region of the second conductivity type provided on the second semiconductor region and having a higher carrier concentration of the second conductivity type than that of the second semiconductor region; and a first electrode provided on the insulating portion and the third semiconductor region, the first electrode having a portion which is aligned with the second semiconductor region in a second direction perpendicular to a first direction being from the first semiconductor region to the second semiconductor region, and the first electrode being in contact with the second semiconductor region and the third semiconductor region.

Abstract: A semiconductor device includes a first-conductivity type first semiconductor region, a gate electrode extending inwardly of the first semiconductor region, a gate insulation layer interposed between the gate electrode and the first semiconductor region, a second-conductivity type second semiconductor region on the first semiconductor region, a first-conductivity type third semiconductor region on selected portions of second semiconductor region, a second-conductivity type fourth semiconductor region on the first semiconductor region and spaced from the second semiconductor region, a first-conductivity type fifth semiconductor region on the fourth semiconductor region, a first insulation layer on the third and fifth semiconductor regions and extending over the gate electrode, a first electrode on the first insulation layer, and a first insulation portion extending between the second and fourth semiconductor regions.

Abstract: A semiconductor device comprising: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided on the first semiconductor region; an insulating portion provided on the first semiconductor region; a third semiconductor region of the second conductivity type provided on the second semiconductor region and having a hicher carrier concentration of the second conductivity type than that of the second semiconductor region; and a first electrode provided on the insulating portion and the third semiconductor region, the first electrode having a portion which is aligned with the second semiconductor region in a second direction perpendicular to a first direction being from the first semiconductor region to the second semiconductor region, and the first electrode being in contact with the second semiconductor region and the third semiconductor region.

Abstract: A transmission device includes an internal device for transmitting a broadcast signal includes a nonvolatile memory, an internal device control section and a CPU. The nonvolatile memory holds setting information about the internal device. The internal device control section reads the setting information from the nonvolatile memory upon power on and controls the internal device on the basis of the setting information. The CPU boots up an OS (Operating System) upon the power on.

Abstract: According to one embodiment, a semiconductor device comprises a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the second conductivity type, a fourth semiconductor region of the second conductivity type, and an insulating unit. The fourth semiconductor region is separated from the third semiconductor region. A carrier concentration of the second conductivity type of the fourth semiconductor region is higher than a carrier concentration of the second conductivity type of the second semiconductor region. The fourth semiconductor region protrudes below more than the third semiconductor region. The insulating unit is provided on a portion of the second semiconductor region positioned between the third semiconductor region and the fourth semiconductor region and on the fourth semiconductor region.

Abstract: According to one embodiment, a semiconductor device includes a first main electrode, a base layer of a first conductivity type, a barrier layer of the first conductivity type, a diffusion layer of a second conductivity type, a base layer of the second conductivity type, a first conductor layer, a second conductor layer, and a second main electrode. Bottoms of the barrier layer of the first conductivity type and the diffusion layer of the second conductivity type are positioned on the first main electrode side of lower ends of the first conductor layer and the second conductor layer. The barrier layer of the first conductivity type and the diffusion layer of the second conductivity type form a super junction proximally to tips of the first conductor layer and the second conductor layer.

Abstract: A semiconductor device includes a semiconductor layer having a first p-type semiconductor region at a first surface and a first n-type semiconductor region at a second surface opposite the first. A second n-type semiconductor region having a n-type dopant concentration lower than the first n-type semiconductor region is between the first p-type and first n-type semiconductor regions. A third n-type semiconductor region is disposed between the second n-type semiconductor region and the first p-type semiconductor region. a fourth n-type semiconductor region is disposed between the first n-type semiconductor region and the second n-type semiconductor region. The fourth n-type semiconductor region has a stored carrier lifetime longer than the third n-type semiconductor region and a crystal lattice defect level is higher in the third n-type semiconductor than in the fourth n-type semiconductor region. An anode is disposed on the first surface and a cathode is disposed on the second surface.

Abstract: A transmission device includes an internal device for transmitting a broadcast signal includes a nonvolatile memory, an internal device control section and a CPU. The nonvolatile memory holds setting information about the internal device. The internal device control section reads the setting information from the nonvolatile memory upon power on and controls the internal device on the basis of the setting information. The CPU boots up an OS (Operating System) upon the power on.

Abstract: According to one embodiment, a semiconductor device includes a main element and a sense element. The main element is connected between a collector terminal and an emitter terminal. The main element has an insulated gate bipolar transistor structure. The sense element is connected in parallel with the main element via a sense resistor between the collector terminal and the emitter terminal. The sense element has an insulated gate bipolar transistor structure with a feedback capacitance larger than a feedback capacitance of the main element.

Abstract: According to one embodiment, a semiconductor device includes a first main electrode, a base layer of a first conductivity type, a barrier layer of the first conductivity type, a diffusion layer of a second conductivity type, a base layer of the second conductivity type, a first conductor layer, a second conductor layer, and a second main electrode. Bottoms of the barrier layer of the first conductivity type and the diffusion layer of the second conductivity type are positioned on the first main electrode side of lower ends of the first conductor layer and the second conductor layer. The barrier layer of the first conductivity type and the diffusion layer of the second conductivity type form a super junction proximally to tips of the first conductor layer and the second conductor layer.

Abstract: According to one embodiment, a semiconductor device includes a first main electrode, a base layer of a first conductivity type, a barrier layer of the first conductivity type, a diffusion layer of a second conductivity type, a base layer of the second conductivity type, a first conductor layer, a second conductor layer, and a second main electrode. Bottoms of the barrier layer of the first conductivity type and the diffusion layer of the second conductivity type are positioned on the first main electrode side of lower ends of the first conductor layer and the second conductor layer. The barrier layer of the first conductivity type and the diffusion layer of the second conductivity type form a super junction proximally to tips of the first conductor layer and the second conductor layer.

Abstract: A body layer of a first conductivity type is formed on a semiconductor substrate, and a source layer of a second conductivity type is formed in a surface region of the body layer. An offset layer of the second conductivity type is formed on the semiconductor substrate, and a drain layer of the second conductivity type is formed in a surface region of the offset layer. An insulating film is embedded in a trench formed in the surface region of the offset layer between the source layer and the drain layer. A gate insulating film is formed on the body layer and the offset layer between the source layer and the insulating film. A gate electrode is formed on the gate insulating film. A first peak of an impurity concentration profile in the offset layer is formed at a position deeper than the insulating film.

Abstract: According to one embodiment, a semiconductor device includes a main element and a sense element. The main element is connected between a collector terminal and an emitter terminal. The main element has an insulated gate bipolar transistor structure. The sense element is connected in parallel with the main element via a sense resistor between the collector terminal and the emitter terminal. The sense element has an insulated gate bipolar transistor structure with a feedback capacitance larger than a feedback capacitance of the main element.

Abstract: According to one embodiment, a semiconductor device includes a first main electrode, a base layer of a first conductivity type, a barrier layer of the first conductivity type, a diffusion layer of a second conductivity type, a base layer of the second conductivity type, a first conductor layer, a second conductor layer, and a second main electrode. The base layer of the first conductivity type is provided on the first main electrode. The barrier layer of the first conductivity type and the diffusion layer of the second conductivity type are provided on the base layer of the first conductivity type. The barrier layer of the first conductivity type and the diffusion layer of the second conductivity type are arranged alternately. The base layer of the second conductivity type is provided on the barrier layer of the first conductivity type.

Abstract: A low resistance layer is formed on a semiconductor substrate, and a high resistance layer formed on the low resistance layer. A source region of a first conductivity type is formed on a surface region of the high resistance layer. A drain region of the first conductivity type is formed at a distance from the source region. A first resurf region of the first conductivity type is formed in a surface region of the high resistance layer between the source region and the drain region. A channel region of a second conductivity type is formed between the source region and the first resurf region. A gate insulating film is formed on the channel region, and a gate electrode formed on the gate insulating film. An impurity concentration in the channel region under the gate electrode gradually lowers from the source region toward the first resurf region.

Abstract: An integrated circuit device includes: a main interconnect; and a coil located on one side of the main interconnect at a position fixed with respect to the main interconnect, the coil having a central axis extending in a direction crossing the extending direction of the main interconnect. An induction current detectable by the coil is generated due to a current flowing through the main interconnect.