Patents by Inventor Kenichi Nomura

Kenichi Nomura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170370924
    Abstract: [Problem] To provide a target substance detection chip, a target substance detection device, and a target substance detection method, that can be manufactured easily in a small size at low costs with reduction of the number of parts involved in the detection chip constituted by an optical prism and a detection plate used for a SPR sensor and an optical waveguide mode sensor, that can detect a target substance quickly with high sensitivity, and in which an analyte liquid is easily delivered.
    Type: Application
    Filed: August 28, 2017
    Publication date: December 28, 2017
    Inventors: Makoto FUJIMAKI, Nobuko FUKUDA, Kenichi NOMURA, Hidenori NAGAI, Toshihiko OOIE
  • Publication number: 20170232705
    Abstract: Provided is an air-permeable sheet (3) to be used in a state of being interposed between a suction stage (1) and an air-impermeable substrate (4) when printing is performed by a sheet-fed method on the surface of the substrate (4) fixed by suction to the suction stage (1), the air-permeable sheet capable of printing a desired printing pattern on the surface of the substrate with high accuracy. The air-permeable sheet (3) includes a non-woven fabric layer (3b) and a support layer (3a) constituted by a woven fabric or knitted fabric.
    Type: Application
    Filed: April 17, 2015
    Publication date: August 17, 2017
    Applicants: Japan Vilene Company, Ltd., National Institute of Advanced Industrial Science and Technology
    Inventors: Kenichi NOMURA, Hirobumi USHIJIMA, Kengo NOGUCHI, Noriko MICHIHATA, Takeshi KOBAYASHI, Masaaki KAWABE
  • Patent number: 9697954
    Abstract: The invention provides a process and an apparatus for producing a high quality electronic component by reducing sagging at pattern side walls, which may occur when patterns of a wiring, an electrode, etc. are printed by a screen printing process using an electroconductive paste, an insulation paste, or a semiconductor paste, and reducing a mesh mark on the patterns of a wiring, an electrode, etc., or a full solid surface film, as well as a pattern formation process, by which screen printing can be applied and double face printing can be conducted with the number of process steps less than a conventional process. A pattern is formed by that a pattern is printed on a blanket having a surface comprising polydimethylsiloxane using an electroconductive paste, an insulation paste, or a semiconductor paste by a screen printing process, and the pattern is transferred from the blanket to a printing object.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: July 4, 2017
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Kenichi Nomura, Hirobumi Ushijima, Noriko Iwase, Manabu Yoshida
  • Publication number: 20170014075
    Abstract: A support tool is mounted on a finger of a subject on whom a sensor is mounted to support acquisition of biological information. A first support is disposed on a nail side of the subject's finger. A second support is disposed on a ventral side of the subject's finger. The relative position of the second support with respect to the first support does not change. A bag is formed with a material softer than the first support and second support, and is disposed along an inner peripheral face of the first support. A ventilation tube forms a ventilation channel communicating with an inside of the bag. The sensor includes a light emission part and a light reception part. The light emission part is disposed between the subject's finger and the bag. The light reception part is disposed between the subject's finger and the second support.
    Type: Application
    Filed: February 27, 2015
    Publication date: January 19, 2017
    Inventors: Naoto MORIMURA, Naoki KOBAYASHI, Katsuyuki HORIE, Hideaki HIRABARA, Katsuyoshi SUZUKI, Wataru MATSUZAWA, Sou KUMAGAI, Katsuhide TONE, Kenichi NOMURA
  • Patent number: 9499553
    Abstract: The present invention provides a dihydropyridazine-3,5-dione derivative or a salt thereof, or a solvate of the compound or the salt, a pharmaceutical drug, a pharmaceutical composition, a sodium-dependent phosphate transporter inhibitor, and a preventive and/or therapeutic agent for hyperphosphatemia, secondary hyperparathyroidism, chronic renal failure, chronic kidney disease, and arteriosclerosis associated with vascular calcification comprising the compound as an active ingredient, and a method for prevention and/or treatment.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: November 22, 2016
    Assignee: CHUGAI SEIYAKU KABUSHIKI KAISHA
    Inventors: Yoshihito Ohtake, Naoki Okamoto, Yoshiyuki Ono, Hirotaka Kashiwagi, Atsushi Kimbara, Takeo Harada, Nobuyuki Hori, Yoshihisa Murata, Kazutaka Tachibana, Shota Tanaka, Kenichi Nomura, Mitsuaki Ide, Eisaku Mizuguchi, Yasuhiro Ichida, Shuichi Ohtomo, Naoshi Horiba
  • Patent number: 9443127
    Abstract: A cell analyzing apparatus includes: a first histogram acquiring section which is configured to acquire a first histogram of fluorescence intensities by using a result of a measurement of a number of nuclear stained cells; a second histogram acquiring section which is configured to acquire a second histogram that is normalized based on a fluorescence intensity value indicating a maximum value of the first histogram; a determining section which is configured to determine whether cancer cells exist or not, based on one of the first histogram and the second histogram; and an outputting section which is configured to output a result of the determination performed by the determining section.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: September 13, 2016
    Assignee: Nihon Kohden Corporation
    Inventors: Sunao Takeda, Hirotsugu Kubo, Takahiro Shioyama, Akane Suzuki, Kenichi Nomura, Yo Kato, Nae Hinata
  • Publication number: 20160233868
    Abstract: A semiconductor integrated circuit includes: a phase locked loop circuit which outputs a clock signal; an internal circuit which executes processing; a capacitor; and a switch circuit which connects the capacitor to either of the phase locked loop circuit and the internal circuit.
    Type: Application
    Filed: April 20, 2016
    Publication date: August 11, 2016
    Inventors: Hiroyuki HOMMA, Kenichi NOMURA, Ryusuke OBARA
  • Publication number: 20160224712
    Abstract: A storage device stores first information indicating a first consumption current value during operation of a first partial circuit included in a circuit under design and second information indicating a surplus current value based on an allowable current value of a power source terminal of a second partial circuit and a second consumption current value during operation of the second partial circuit. A design support apparatus compares the surplus current value and the first consumption current value. When determining that the surplus current value is the first consumption current value or greater, the design support apparatus controls a layout apparatus to generate circuit information for a circuit under design where a power-supplying terminal of the second partial circuit and a power source terminal of the first partial circuit are connected.
    Type: Application
    Filed: April 12, 2016
    Publication date: August 4, 2016
    Applicant: Socionext Inc.
    Inventor: Kenichi NOMURA
  • Publication number: 20160217237
    Abstract: A processor detects a phase difference between a feedback clock and a reference clock of a PLL circuit, generates, based on the phase difference, first frequency information indicating a candidate value of a frequency of an output clock being output from the PLL circuit, generates second frequency information by smoothing the first frequency information, and generates the output clock by determining the frequency based on the second
    Type: Application
    Filed: January 6, 2016
    Publication date: July 28, 2016
    Inventors: Hitoshi Kurosu, Kenichi NOMURA
  • Publication number: 20160002251
    Abstract: The present invention provides a dihydropyridazine-3,5-dione derivative or a salt thereof, or a solvate of the compound or the salt, a pharmaceutical drug, a pharmaceutical composition, a sodium-dependent phosphate transporter inhibitor, and a preventive and/or therapeutic agent for hyperphosphatemia, secondary hyperparathyroidism, chronic renal failure, chronic kidney disease, and arteriosclerosis associated with vascular calcification comprising the compound as an active ingredient, and a method for prevention and/or treatment.
    Type: Application
    Filed: September 14, 2015
    Publication date: January 7, 2016
    Inventors: Yoshihito OHTAKE, Naoki OKAMOTO, Yoshiyuki ONO, Hirotaka KASHIWAGI, Atsushi KIMBARA, Takeo HARADA, Nobuyuki HORI, Yoshihisa MURATA, Kazutaka TACHIBANA, Shota TANAKA, Kenichi NOMURA, Mitsuaki IDE, Eisaku MIZUGUCHI, Yasuhiro ICHIDA, Shuichi OHTOMO, Naoshi HORIBA
  • Publication number: 20150243441
    Abstract: The invention provides a process and an apparatus for producing a high quality electronic component by reducing sagging at pattern side walls, which may occur when patterns of a wiring, an electrode, etc. are printed by a screen printing process using an electroconductive paste, an insulation paste, or a semiconductor paste, and reducing a mesh mark on the patterns of a wiring, an electrode, etc., or a full solid surface film, as well as a pattern formation process, by which screen printing can be applied and double face printing can be conducted with the number of process steps less than a conventional process. A pattern is formed by that a pattern is printed on a blanket having a surface comprising polydimethylsiloxane using an electroconductive paste, an insulation paste, or a semiconductor paste by a screen printing process, and the pattern is transferred from the blanket to a printing object.
    Type: Application
    Filed: September 11, 2013
    Publication date: August 27, 2015
    Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Kenichi Nomura, Hirobumi Ushijima, Noriko Iwase, Manabu Yoshida
  • Publication number: 20150078649
    Abstract: A cell analyzing apparatus includes: a first histogram acquiring section which is configured to acquire a first histogram of fluorescence intensities by using a result of a measurement of a number of nuclear stained cells; a second histogram acquiring section which is configured to acquire a second histogram that is normalized based on a fluorescence intensity value indicating a maximum value of the first histogram; a determining section which is configured to determine whether cancer cells exist or not, based on one of the first histogram and the second histogram; and an outputting section which is configured to output a result of the determination performed by the determining section.
    Type: Application
    Filed: September 17, 2014
    Publication date: March 19, 2015
    Applicant: Nihon Kohden Corporation
    Inventors: Sunao TAKEDA, Hirotsugu KUBO, Takahiro SHIOYAMA, Akane SUZUKI, Kenichi NOMURA, Yo KATO, Nae HINATA
  • Patent number: 8825463
    Abstract: A logic simulation method includes causing a physical specification detector to detect physical specifications of an analog circuit (a PLL circuit and a DLL circuit) as a verification object described in a logic library; causing a monitor to monitor whether a signal or setting during a logic simulation satisfies the physical specifications; and causing a warning section to issue a warning when the signal or the setting fails to satisfy the physical specifications.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: September 2, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kenichi Nomura, Hideaki Anbutsu, Cheng Giam Tan
  • Publication number: 20140170024
    Abstract: [Problem] To provide a target substance detection chip, a target substance detection device, and a target substance detection method, that can be manufactured easily in a small size at low costs with reduction of the number of parts involved in the detection chip constituted by an optical prism and a detection plate used for a SPR sensor and an optical waveguide mode sensor, that can detect a target substance quickly with high sensitivity, and in which an analyte liquid is easily delivered.
    Type: Application
    Filed: July 3, 2012
    Publication date: June 19, 2014
    Applicant: National Institute of Advanced Industrial Science and Technology
    Inventors: Makoto Fujimaki, Nobuko Fukuda, Kenichi Nomura, Hidenori Nagai, Toshihiko Ooie
  • Publication number: 20110312103
    Abstract: The present invention uses a detecting plate having a transparent substrate on which a single-crystal Si thin film layer, a transparent thin film layer, and a sample capturing layer for capturing a sample are provided. The present invention comprises a light directing mechanism for directing light through said transparent substrate of the detecting plate, and a light detection mechanism for detecting reflected light of the incident light from the detecting plate. The present invention is configured so that a change in absorbance occurs at the sample capturing layer or in the vicinity thereof, when said sample is captured on said sample capturing layer. The wavelengths of said incident light are determined in a range of wavelengths within which said change in absorbance occurs. In this way, the sample is detected by means of measuring a significant change in intensity of the reflected light which is generated when the sample is captured on the sample capturing layer.
    Type: Application
    Filed: December 18, 2009
    Publication date: December 22, 2011
    Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Makoto Fujimaki, Kenichi Nomura
  • Patent number: 7750710
    Abstract: A delay circuit has a second delay element 8 supplied with a delay time control signal Vcntl from a frequency variable oscillator 2 including a first delay element 8 of which delay time as a concomitant of signal propagation is controlled by a delay time control signal and a phase inverting element 9 inverting a phase of the signal, and an adjusting element 10, connected in series to the second delay element 8, to which the signal is propagated, wherein a total of the delay time of the second delay element 8 and the delay time of the adjusting element 10 is adjusted.
    Type: Grant
    Filed: November 3, 2005
    Date of Patent: July 6, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventor: Kenichi Nomura
  • Publication number: 20090326902
    Abstract: A logic simulation method includes causing a physical specification detector to detect physical specifications of an analog circuit (a PLL circuit and a DLL circuit) as a verification object described in a logic library; causing a monitor to monitor whether a signal or setting during a logic simulation satisfies the physical specifications; and causing a warning section to issue a warning when the signal or the setting fails to satisfy the physical specifications.
    Type: Application
    Filed: September 2, 2009
    Publication date: December 31, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Kenichi Nomura, Hideaki Anbutsu, Cheng Giam Tan
  • Patent number: 7363908
    Abstract: An electric parts attaching structure for a throttle body includes: a throttle body (12) having an intake passage (16) in which a throttle valve (24) is arranged, and a housing (20) for accommodating electric parts formed on the outside thereof; an intake passage information detection sensor (43) which is attached to a bottom section (42) of said housing (20) for detecting information in said intake passage (16); and a circuit board (45) which is disposed on a side opposite to a side facing the bottom section (42), of said intake passage information detection sensor (43), and is attached to said housing (20) in state where connection pins (89) extending from the intake passage information detection sensor (43), are inserted into connection holes (100).
    Type: Grant
    Filed: March 17, 2004
    Date of Patent: April 29, 2008
    Assignee: Keihin Corporation
    Inventors: Toshiaki Chida, Satoshi Chida, Kenichi Nomura
  • Publication number: 20070013427
    Abstract: A delay circuit has a second delay element 8 supplied with a delay time control signal Vcntl from a frequency variable oscillator 2 including a first delay element 8 of which delay time as a concomitant of signal propagation is controlled by a delay time control signal and a phase inverting element 9 inverting a phase of the signal, and an adjusting element 10, connected in series to the second delay element 8, to which the signal is propagated, wherein a total of the delay time of the second delay element 8 and the delay time of the adjusting element 10 is adjusted.
    Type: Application
    Filed: November 3, 2005
    Publication date: January 18, 2007
    Inventor: Kenichi Nomura
  • Publication number: 20060169248
    Abstract: An electric parts attaching structure for a throttle body includes: a throttle body (12) having an intake passage (16) in which a throttle valve (24) is arranged, and a housing (20) for accommodating electric parts formed on the outside thereof, an intake passage information detection sensor (43) which is attached to a bottom section (42) of said housing (20) for detecting information in said intake passage (16); and a circuit board (45) which is disposed on a side opposite to a side facing the bottom section (42), of said intake passage information detection sensor (43), and is attached to said housing (20) in state where connection pins (89) extending from the intake passage information detection sensor (43), are inserted into connection holes (100).
    Type: Application
    Filed: March 17, 2004
    Publication date: August 3, 2006
    Inventors: Toshiaki Chida, Satoshi Chida, Kenichi Nomura