Abstract: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.

Abstract: The present invention provides an in-vehicle processing device and an in-vehicle system capable of reducing power consumption while suppressing quality degradation of data to be transmitted and received. An ECU includes a data transmission and reception device for transmitting and receiving data and an MPU for controlling the data transmission and reception device. The data transmission and reception device includes a filter device and a steady current suppression circuit. The filter device attenuates noise that is superimposed on data by reflection of the data. The steady current suppression circuit suppresses a steady current flowing through the filter device and facilitates a transient current flowing through the filter device.

Abstract: The autonomous driving ECU includes a first communication unit that transmits and receives autonomous driving data to and from the plurality of data ECUs, and a vehicle control unit that controls a vehicle on the basis of the autonomous driving data transmitted from the plurality of data ECUs. Each data ECU includes a data construction unit that performs a construction of the autonomous driving data transmitted to the autonomous driving ECU, and a second communication unit that transmits and receives the autonomous driving data to and from the autonomous driving ECU. If a predetermined event occurs, among the data ECUs, the data construction unit of the data ECU in which the predetermined event occurs constructs the autonomous driving data so that a total amount of the autonomous driving data transmitted from the data ECU in which the predetermined event occurs is not greater than a predetermined amount of data.

Abstract: Provided are a relay device and the like with which it is possible to suppress bus signal reflections and suppress signal delays. A relay device 100A includes a signal processing and forwarding pathway P1 and a bypass connection pathway P2. The signal processing and forwarding pathway P1 processes a signal received from one bus CAN1 of a plurality of buses, and forwards the processed signal to another bus CAN2. The bypass connection pathway P2 connects the one bus CAN1 to the other bus CAN2, bypassing the signal processing and forwarding pathway P1.

Abstract: Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.

Abstract: A conventional power supply device has a problem in miniaturization. A power supply device generates a prediction value of an error signal from first and second error signals, and controls an output voltage so that the prediction value lies between first and second threshold values. The first error signal is obtained by converting an error voltage based on the difference between the output voltage and a reference voltage at a first timing. The second error signal is obtained by converting an error voltage based on the difference between the output voltage and the reference voltage at a second timing.

Abstract: The gateway device includes a plurality of communication ports that are connected to the respective low-level networks and receive low-level data that is transmitted and received to and from the low-level networks; a storage unit that stores each of the plurality of communication ports and a source identifier in association with each other; and a control unit that generates high-level data and transmits the high-level data to the high-level network, in which the payload of the high-level data that is generated by the control unit includes at least a part of the low-level data that is received by the communication ports, and in which the header of the high-level data that is generated by the control unit includes the source identifier which is associated with the communication ports.

Abstract: When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.

Abstract: Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.

Abstract: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.

Abstract: A conventional power supply device has a problem in miniaturization. A power supply device generates a prediction value of an error signal from first and second error signals, and controls an output voltage so that the prediction value lies between first and second threshold values. The first error signal is obtained by converting an error voltage based on the difference between the output voltage and a reference voltage at a first timing. The second error signal is obtained by converting an error voltage based on the difference between the output voltage and the reference voltage at a second timing.

Abstract: A semiconductor device having static memory cells is designed to reduce leakage current and power consumption. The static memory cells are coupled to word lines and bit lines, and the word lines are coupled to word drivers. A first P channel MOS transistor (MOS power switch) has a gate coupled to receive a first control signal, and a second P channel MOS transistor (MOS power switch) has a gate coupled to receive a second control signal different from the first control signal. Source-drain paths of the first and second P channel MOS transistors (MOS power switches) are coupled to respective voltage supply points for different parts of the semiconductor device, such as voltage supply points for the memory cells and the word drivers, or voltage supply points for a logic circuit and the word drivers.

Abstract: A semiconductor integrated circuit device has a memory array including SRAM cells, a plurality of sense amplifiers for reading out data stored in the SRAM cells and a plurality of MOSFETS. The MOSFETs are controlled by a control signal to be in one of an active state or a standby state. Part of the MOSFETs are arranged along one end of the memory array and the other parts of the MOSFETs are arranged along another end of the memory array. The other end of the memory array is opposite to the one end of the memory array. The MOSFETs are controlled by the control signal to be turned ON in the active state and to be turned OFF in the standby mode.

Abstract: Downsizing of an inductor is achieved while reducing radiation noise of an inductor current. A boosting power supply unit is, for example, provided in an ECU mounted in a vehicle or the like. The boosting power supply unit has a boosting coil, a switching element and a current control unit 16. The current control unit 16 controls the switching element 12 to turn on and off by using a clock signal CK1 with a higher frequency than a pulse signal SPL in a clamping period when the inductor current flowing in the boosting coil is clamped at a preset peak setting current, and controls the switching element to turn on and off by using the pulse signal SPL in periods other than the clamping period. By controlling the switching element to turn on and off in this manner, the inductor current flowing in the boosting coil is controlled.

Abstract: In a semiconductor device in which components to be a basic configuration unit are arranged in an array shape for calculating an interaction model, a technique capable of changing a topology between the components is provided. A semiconductor device includes a plurality of units each of which includes a first memory cell for storing a value indicating a state of one node of an interaction model, a second memory cell for storing an interaction coefficient indicating an interaction from a node connected to the one node, and a calculation circuit for determining a value indicating a next state of the one node based on a value indicating a state of the connected node and on the interaction coefficient. In addition, the semiconductor device includes a plurality of switches for connecting or disconnecting the plurality of units to/from each other.

Abstract: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.

Abstract: A conventional power supply device has a problem in miniaturization. A power supply device generates a prediction value of an error signal from first and second error signals, and controls an output voltage so that the prediction value lies between first and second threshold values. The first error signal is obtained by converting an error voltage based on the difference between the output voltage and a reference voltage at a first timing. The second error signal is obtained by converting an error voltage based on the difference between the output voltage and the reference voltage at a second timing.

Abstract: Downsizing of an inductor is achieved while reducing radiation noise of an inductor current. A boosting power supply unit is, for example, provided in an ECU mounted in a vehicle or the like. The boosting power supply unit has a boosting coil, a switching element and a current control unit 16. The current control unit 16 controls the switching element 12 to turn on and off by using a clock signal CK1 with a higher frequency than a pulse signal SPL in a clamping period when the inductor current flowing in the boosting coil is clamped at a preset peak setting current, and controls the switching element to turn on and off by using the pulse signal SPL in periods other than the clamping period. By controlling the switching element to turn on and off in this manner, the inductor current flowing in the boosting coil is controlled.

Abstract: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.

Abstract: Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.