Abstract: A method and apparatus for executing instructions in a pipeline processor. The method decreases the latency between an instruction cache and a pipeline processor when bubbles occur in the processing stream due to an execution of a branch correction, or when an interrupt changes the sequence of an instruction stream. The latency is reduced when a decode stage for detecting branch prediction and a related instruction queue location have invalid data representing a bubble in the processing stream. Instructions for execution are inserted in parallel into the decode stage and instruction queue, thereby reducing by one cycle time the length of the pipeline stage.

Abstract: A system for at-functional-clock-speed continuous scan array built-in self testing (ABIST) of multiport memory is disclosed. During ABIST testing, functional addressing latches from a first port are used as shadow latches for a second port's addressing latches. The arrangement reduces the amount of test-only hardware on a chip and reduces the need to write complex testing software. Higher level functions may be inserted between the shadow latches and the addressing latches to automatically provide functions such as inversions.

Abstract: An information device, an information device, an information server, an information processing system, an information processing method and an information processing program which can prevent an illegal extension of an expiration date while allowing the same user to redownload a license are provided. An information server (4) includes a license storage means for storing a relative time license, a time obtaining means for obtaining the present time, a license generation means for generating an absolute time license on the basis of the relative time license and the present time before the first transmission of a license to an information device, and a transmission means for transmitting the generated absolute time license to the information device. Even in the case where a license for contents is repeatedly downloaded, irrespective of the time of downloading, the expiration date of the contents can be fixed.

Abstract: A method and processor for reducing the fetch time of target instructions of a predicted taken branch instruction. Each entry in a buffer, referred to herein as a “branch target buffer”, may store an address of a branch instruction predicted taken and the instructions beginning at the target address of the branch instruction predicted taken. When an instruction is fetched from the instruction cache, a particular entry in the branch target buffer is indexed using particular bits of the fetched instruction. The address of the branch instruction in the indexed entry is compared with the address of the instruction fetched from the instruction cache. If there is a match, then the instructions beginning at the target address of that branch instruction are dispatched directly behind the branch instruction. In this manner, the fetch time of target instructions of a predicted taken branch instruction is reduced.

Abstract: Method and apparatus for reformatting instructions in a pipelined processor. An instruction register holds a plurality of instructions received from a cache memory external to the processor. A predecoder predecodes each of the instructions and determines from an instruction operation field where the instruction fields should be placed. A multiplexer reformats architecturally aligned instructions into hardware implementation aligned instructions prior to storing into L1 cache, so that the instructions are ready for dispatch to the pipeline execution units.

Abstract: A protruding section facing a drive pinion shaft is integrally provided on (or provided as a separate component) a tubular spacer interposed between an inner race of a pilot bearing and an inner race of a tapered roller bearing at an inner section opposite to the drive pinion shaft. In one embodiment, a monolithic protruding section is curved so as to be convex along the overall central axial direction of the spacer, and is arch shaped in cross section. The protruding section protrudes towards the drive pinion shaft along the overall inner peripheral direction of the spacer, and the inner surface of the protruding section comes into contact with or close to the outer surface of the drive pinion shaft. Additional positions include one or a plurality of O-rings interposed between the drive pinion shaft and the inner surface of the tubular spacer.

Abstract: An LRU array and method for tracking the accessing of lines of an associative cache. The most recently accessed lines of the cache are identified in the table, and cache lines can be blocked from being replaced. The LRU array contains a data array having a row of data representing each line of the associative cache, having a common address portion. A first set of data for the cache line identifies the relative age of the cache line for each way with respect to every other way. A second set of data identifies whether a line of one of the ways is not to be replaced. For cache line replacement, the cache controller will select the least recently accessed line using contents of the LRU array, considering the value of the first set of data, as well as the value of the second set of data indicating whether or not a way is locked. Updates to the LRU occur after each pre-fetch or fetch of a line or when it replaces another line in the cache memory.

Abstract: A processor supports logical partitioning of hardware resources including real address spaces of a computer system. An ultra-privileged supervisor process, called a hypervisor, regulates the logical partitions and can dynamically re-allocate resources. Preferably, the processor supports hardware multithreading, each thread independently capable of being in either hypervisor, supervisor, or problem state, and is capable of entering hypervisor state only upon occurrence of certain pre-defined events. A logical partition identifier is stored in a processor register, and can be altered by the processor only when in hypervisor state. Certain bus communications contain a logical partition identifier tag, and the processor ignores such communications if the tag does not match its own logical partition identifier in its register.

Abstract: A processor contains multiple levels of registers having different access latency. A relatively smaller set of registers is contained in a relatively faster higher level register bank, and a larger, more complete set of the registers is contained in a relatively slower lower level register bank. Physically, the higher level register bank is placed closer to functional logic which receives inputs from the registers. Preferably, the lower level bank includes a complete set of all processor registers, and the higher level bank includes a smaller subset of the registers, duplicating information in the lower level bank. The higher level bank is preferably accessible in a single clock cycle.

Abstract: A metal thin film provided on a substrate and having a metal with a face-centered cubic crystal structure, wherein the metal thin film is preferentially oriented in a (111) plane, and a (100) plane which is not parallel to a surface of the substrate is present on a surface of the thin film. In this metal thin film, the metal with a face-centered cubic crystal structure includes at least one element selected from the group consisting of Pt, Ir, and Ru.

Abstract: Provided are an information device, an information server, an information processing system, an information processing method and an information processing program enabling a user who obtains a content in a legitimate manner to use the content in any other information device owned by the user. An information server (4) associates a user with information devices (1-1 through 1-3) owned by the user to control them, and the same service data (a leaf ID and key information DNK) is written in the information devices owned by the same user to treat a plurality of information devices owned by the user as one group. As a result, a content obtained by the information device (1-1) owned by the user can be used in other information devices (1-2, 1-3) owned by the user. Moreover, the content can be used in the information devices through directly transferring the content or a license between the information devices (1-1 through 1-3).

Abstract: A content distributing system for distributing content disclosed herein is an encrypting apparatus for encrypting each of objects constituting content using a different encryption key, a content offering apparatus for offering the encrypted content to a content reproducing apparatus; a license information offering apparatus for offering license information including information necessary for decrypting the encrypted content, and a content reproducing apparatus for acquiring the encrypted content from the content offering apparatus in order to decrypt and reproduce the acquired content using the license information acquired from the license offering apparatus.

Abstract: A method and apparatus for executing instructions in a pipeline processor. The method decreases the latency between an instruction cache and a pipeline processor when bubbles occur in the processing stream due to an execution of a branch correction, or when an interrupt changes the sequence of an instruction stream. The latency is reduced when a decode stage for detecting branch prediction and a related instruction queue location have invalid data representing a bubble in the processing stream. Instructions for execution are inserted in parallel into the decode stage and instruction queue, thereby reducing by one cycle time the length of the pipeline stage.

Abstract: An electrically conductive roll includes a shaft body and at least a conductive elastic layer formed by extrusion on an outer circumferential surface of the shaft body. The conductive elastic layer is formed from at least one conductive rubber composition which includes a rubber material, a thermoplastic resin having crosslinkable double bonds and a melting point in a range from 40° C. to 100° C., and at least one conductive agent. The thermoplastic resin is included in an amount of 5 to 50 wt. % of a total amount of the rubber material and the thermoplastic resin.

Abstract: An electrically conductive roll includes a center shaft, an electrically conductive elastic layer formed on an outer circumferential surface of the center shaft, and a resistance adjusting layer formed radially outwardly of the electrically conductive elastic layer. The resistance adjusting layer is formed of a rubber composition which includes a rubber material, a thermoplastic resin having crosslinkable double bonds, at least one electron-conductive agent, at least one ion-conductive agent, and at least one electrically insulating filler. The thermoplastic resin, the at least one electron-conductive agent, the at least one ion-conductive agent, and the at least one electrically insulating filler are included in the rubber composition in respective amounts of 3-40 parts by weight, 10-150 parts by weight, not greater than 2 parts by weight, and 20-80 parts by weight, per 100 parts by weight of the rubber material.

Abstract: A processor supports logical partitioning of hardware resources including real address spaces of a computer system. An ultra-privileged supervisor process, called a hypervisor, regulates the logical partitions and can dynamically re-allocate resources. Preferably, the processor supports hardware multithreading, each thread independently capable of being in either hypervisor, supervisor, or problem state, and is capable of entering hypervisor state only upon occurrence of certain pre-defined events. A logical partition identifier is stored in a processor register, and can be altered by the processor only when in hypervisor state. Certain bus communications contain a logical partition identifier tag, and the processor ignores such communications if the tag does not match its own logical partition identifier in its register.

Abstract: A real address range check mechanism verifies real addresses generated in a computer system which translates real addresses from effective addresses, some of the effective addresses being real addresses not requiring translation. The system has at least two operating modes. In one mode, the range checking mechanism generates an error signal responsive to detecting a real address outside a predetermined range, and in the other operating mode no error signal is generated. Preferably, the computer system's hardware resources, including real address space, is logically partitioned, partitioning being managed by an ultra-privileged process called a hypervisor. Preferably, the processor supports hardware multithreading, each thread independently capable of being in either hypervisor, supervisor, or problem state, real address range checking error signals being disabled in the hypervisor state.

Abstract: An electrically conductive roll which includes a shaft body and which includes at least a conductive elastic layer formed by extrusion on an outer circumferential surface of the shaft body, wherein the conductive elastic layer is formed of at least one conductive rubber composition which includes a rubber material, a thermoplastic resin having crosslinkable double bonds and a melting point in a range from 40° C. to 100° C., and at least one conductive agent, the thermoplastic resin being included in an amount of 5 to 50 wt. % of a total amount of the rubber material and the thermoplastic resin.

Abstract: An electrically conductive roll including a center shaft, an electrically conductive elastic layer formed on an outer circumferential surface of the center shaft, and a resistance adjusting layer formed radially outwardly of the electrically conductive elastic layer, wherein the resistance adjusting layer is formed of a rubber composition which includes a rubber material, a thermoplastic resin having crosslinkable double bonds, at least one electron-conductive agent, at least one ion-conductive agent, and at least one electrically insulating filler, the thermoplastic resin, the at least one electron-conductive agent, the at least one ion-conductive agent, and the at least one electrically insulating filler being included in the rubber composition in respective amounts of 3-40 parts by weight, 10-150 parts by weight, not greater than 2 parts by weight, and 20-80 parts by weight, per 100 parts by weight of the rubber material.

Abstract: The present invention provides three insertion elements and transposases encoded by the insertion elements that are derived from the genome of Ralstonia solanacearum, which has been isolated with a transposon trap vector.