Abstract: An information processing apparatus having a buffer register for pre-fetching a plurality of instructions and executing one instruction after another by reading them from the buffer registers, is provided with a first instruction decode start determination unit for register type instructions and a second instruction decode start determination unit for non-register type instructions, provided separately from the first unit, whereby 0.5 cycle after a register type instruction starts being decoded, or 1 cycle after a non-register type instruction starts being decoded, the next instruction starts to be decoded. By decoding a register type instruction at high speed, it becomes possible to execute a branch instruction at high speed.

Abstract: A decimal multiplier device including a register A storing the multiplier, a register B storing the multiplicand, a shifter for outputting the output of the register A as it is or after having been shifted, based on a first signal, a gate for outputting the output of the register B or "0", based on a second signal, an adder/subtractor for adding the output of the shifter and that of the gate and storing the result thus obtained in the register A, and a decoder for receiving the value of a selected digit of the content of the register A and controlling the gate and the shifter by generating the first signal and the second signal based on the received value so that the multiplicand B is added n times, n corresponding to the received value, to the content of the register A or substracted (10-n) times therefrom. The register A, the shifter and the adder/subtractor form a single loop. Decimal multiplication is performed by controlling the shifter, when signals pass through the loop repeatedly.

Abstract: A data processing system for executing an instruction in a plurality of stages in a pipeline mode comprises a main operation unit capable of executing all instructions to be executed in the data processing system, a pre-operation unit capable of executing instructions which occurs at a high frequency and can be executed with a small number of circuit components, general purpose registers for storing operation results of the instructions, and a control unit for controlling the writing of the operation results by the main operation unit and the pre-operation unit into the general purpose registers.

Abstract: This invention employs a construction in which subtraction processing and digit shift processing in decimal division are carried out in parallel with each other to shorten the time required for decimal division.A dividend is stored in a register B and a divisor, in a register C. A selector 6 selects register B when the result of subtraction by an adder/subtracter 1 is positive or zero, and selects register A at other times. Both adder/subtracter 1 and a shifter 2 receive the signal from the selector 6 in the same way, and execute the subtraction processing and the shift processing, respectively. The results of these processings are stored in the registers B and A', respectively.The division time can be shortened because the adder/subtracter 1 and the shifter 2 can be actuated simultaneously.

Abstract: An electrically conductive titanate derivative containing an element other than titanium is prepared by baking a mixture of a titanate and a compound containing an element other than titanium.

Abstract: A process for preparing a metamorphosed metal oxide, which comprises heating, under a non-oxidative (and not hydrogenous) atmosphere, a mixture of at least one metal oxide, said metal being selected from the group consisting of elements of Groups III, IV, V and II b and transition elements in Periodic Table, and a carbide represented by the formula:C(M).sub.zwherein M is an element except carbon selected from the group consisting of elements of Groups III, IV and V in Periodic Table, and Z is an integer corresponding to the valency of M, is disclosed. The process is simple and safe and the metamorphosed metal oxide obtained is modified in color tint and provided with electroconductivity.

Abstract: An arithmetic system includes an arithmetic unit of a pipeline structure for executing arithmetic operations for instructions which require different arithmetic cycles. The arithmetic unit executes N arithmetics in pipeline for N instruction at maximum. Initiation of arithmetic operation for a new instruction in the arithmetic unit is indicated by an indicator which detects that each of the instruction executed in the arithmetic is N cycles before completion of the execution and allows arithmetic operation for the new instruction to be initiated in the succeeding cycle.

Abstract: In a storage hierarchy system, a part of data stored in a main storage in held as a copy by a buffer storage of a smaller capacity and higher speed than the main storage. A processor fetches data from the buffer storage or stores data in the buffer storage at a high speed. A buffer storage control system includes a first buffer directory and a second buffer directory. The first buffer directory and the buffer storage are accessed by an address for a fetch request, while the second buffer directory and the buffer storage are accessed by an address for store request, whereby competition for the access to the buffer storage between the fetch and store operations is reduced.

Abstract: A process for preparing metamorphosed alkaline metal titanates which comprises heating a mixture of at least one alkaline metal compound capable of being decomposed into an oxide of the alkaline metal and a gas by heating, and titanium dioxide, under a non-oxidative atmosphere, in the presence of at least one carbide represented by the formulaC(M).sub.z (1)wherein M is an element except carbon selected from groups III, IV and V in Periodic Table, and z is an integer corresponding to valency of M.The products have excellent heat resistance and electroconductivity and are useful as insulating materials.

Abstract: In a buffer storage device where swapping of data is employed, plural candidates for replacement of data in a buffer are determined in response to any access to the buffer storage, and, when the replacement is required, one of the candidates is selected so that processing time for replacement can be minimum.

Abstract: A duplex copying apparatus is provided in the space therebelow with a duplex copying auxiliary means for returning a sheet having an original copied thereon to a sheet feed path extending from a sheet discharge station of the copying apparatus to an image formation station of the apparatus. A support unit for exclusive use in the copying apparatus is detachably provided with a copied sheet return station of the duplex copying auxiliary means.

Abstract: A copy machine having an image forming section includes a paper transport passage to such section, a turn-over guide portion which turns over the sheet formed and recorded with an image on its one surface for feeding-in, and a sheet return for returning the sheet formed and recorded with the image on its one surface, from a paper discharge section towards the turn-over guide portion. And, with each one sheet or n (n.gtoreq.2) sheets being set as one group, each of the sheets recorded on its one surface per each group, is returned to the paper feeding transport passage for effecting image formation and recording onto its other surface. The sheet returning speed is set to be either faster than the ordinary transport speed at the image forming section or to be variable so as to eliminate a loss in time during recording to the other surface of the sheet after recording onto the one surface thereof.

Abstract: A data processing system for executing an instruction in a plurality of stages in a pipeline mode comprises a main operation unit for operating all instructions to be executed by the data processing unit, a first group of general purpose registers for storing the operation results of the main operation unit, a pre-operation unit for operating a portion of instructions which frequently appear and which can be operated with a small number of circuit components, a second group of general purpose registers for storing the operation results of the pre-operation unit, and control means for storing the operation result of the pre-operation unit into the second general purpose register at least one operation stage earlier than the storing of the operation result of the main operation unit into the first general purpose register and storing the contents of the second general purpose registers into the first general purpose registers when an interruption occurs.

Abstract: In a data processing apparatus executing a plurality of instructions in a pipeline mode by dividing each of the instructions into a plurality of stages, its operation circuit includes a first execution (E) unit capable of execution of operations required by all of the plural instructions and a second E unit capable of execution of operations required by part of the plural instructions only. A queue of data including decoded information of the instructions required for execution of operation stages are stored in a circuit to be selectively supplied by first and second circuits to the first and second E units, respectively. The first and second circuits sequentially select succeeding data in synchronism with the end of operations in the first and second E units respectively.

Abstract: An improved method of controlling toner concentration for electrophotographic copying apparatus employing a dual component developing material which is composed of toner particles and magnetic particles. The method is arranged to detect the amount of magnetic particles adhering onto a photosensitive member for controlling the toner replenishing amount according to the amount of the magnetic particles thus detected.

Abstract: A data processing system in which a scan-in operation is initiated to scan in data for giving rise to occurrence of pseudo-failure in response to an address coincidence signal representative of a pseudo-failure signal. A one-shot suppression pulse signal is issued for inhibiting temporarily operation execution during a time span between the scan-in and the occurrence of failure.

Abstract: A both surface recording apparatus for a copying machine includes an image forming section for forming and recording an image on one surface of each sheet, which includes, on a paper transport passage to the image forming section, a turn-over guide portion for turning over and feeding-in each sheet after having been recorded on its one surface. A passage change-over section formed into a unit is attachable to and detachable from the apparatus, and is arranged to guide the sheet formed and recorded with the image at the image forming portion, through change-over either into a passage for discharging the sheet out of the apparatus or into a passage for returning the sheet to the turn-over guide portion.

Abstract: An electrographic developing apparatus having incorporated therein a toner supply device by which the toner concentration of the developer accommodated in a developer container can be maintained at a constant value substantially without requiring any toner concentration detector. The device has a toner tank having a bottom adapted to be contacted by the developer contained in a toner supply section of the container, and a developer moving device for forcibly moving a portion of the developer contained in a developing section of the container into the toner supply section when replenishing toner is dispensed from the tank.

Abstract: An information processing system having an instruction unit for decoding each of successive instructions to generate an address of a next instruction, and additionally, when a branch instruction is decoded, a branch-to address of the decoded branch instruction. An execution unit sequentially executes the decoded instructions and a plurality of registers are provided for storing the next instruction address and the branch-to address. A pointer is generated to indicate one of the registers in which the next instruction address or the branch-to address is to be stored and the pointer is changed sequentially and cyclically in response to a first signal which is generated by the execution unit upon completion of execution of each decoded instruction or a second signal which is generated by the execution unit upon success in branch when a branch instruction is executed. Further provided is a delay circuit for receiving the pointer and generating it at a predetermined time delay.

Abstract: A data processing system is disclosed in which it is detected whether or not data to be read out from a buffer memory with a single access are spread over a plurality of blocks, which are used as the unit for storing data in the buffer memory, and, when the presence of block cross is detected, addresses of blocks including a desired operand are generated as addresses in banks making up the buffer memory, whereby the operand is read out from adjacent blocks by a single read-out operation.