Patents by Inventor Kenji Aoyama

Kenji Aoyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250080015
    Abstract: A controller 1 is provided with: a motor controller (10, 11, etc.) that supplies a drive current to a motor 3, which is a power source of a processing device so as to place the motor 3 in a normal operating state, and, in response to multiplexed commands (S1, S2) that are sent from outside and relate to a safety function operation of the processing device, controls the drive current so as to place the motor 3 and the processing device in a safety stop state; and a command monitoring unit 16 that monitors whether or not the commands (High/Low of S1, S2) match each other. If a period during which the commands do not match exceeds an allowable value, the command monitoring unit 16 generates a safety stop signal Sd (High) for safely stopping the motor 3, and continuously sends the safety stop signal Sd (High) to the motor controller. This configuration makes it possible to facilitate construction of a safety system that uses the controller.
    Type: Application
    Filed: January 26, 2022
    Publication date: March 6, 2025
    Inventors: Kenji TAKEDA, Tomoyuki AOYAMA, Junnosuke IMURA
  • Patent number: 12240993
    Abstract: To provide an article with a water and oil repellent layer, which is excellent in friction resistance. The article with a water and oil repellent layer of the present invention comprises a substrate, a water and oil repellent layer consisting of a hydrolyzed condensation product of a compound represented by the formula [A-(OX)m-]jY1[—Si(R)nL3-n]g, and a silicon oxide layer containing alkali metal atoms that exists between the substrate and the water and oil repellent layer, wherein the average value of the concentration of alkali metal atoms in a predetermined area in the silicon oxide layer is at least a predetermined value. In the formula, X is a fluoroalkylene group, m is at least 2, j, g, and k are at least 1, and Y1 and Y2 are linking groups, R is a monovalent hydrocarbon group, L is a hydrolyzable group or hydroxy group, n is 0 to 2, A is a perfluoroalkyl group or —Y2[—Si(R)nL3-n]n. When A is —Y2[—Si(R)nL3-n]k, j is 1, and when A is a perfluoroalkyl group and j is 1, g is at least 2.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: March 4, 2025
    Assignee: AGC Inc.
    Inventors: Yusuke Tomiyori, Motoshi Aoyama, Kenji Ishizeki
  • Publication number: 20240276721
    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of conductor layers including a first conductor layer as an uppermost layer; a plurality of memory pillars penetrating the conductor layers; and a member that includes a first portion extending in the conductor layers and a plurality of second portions RT provided apart from each other on the uppermost layer side of the conductor layers, and divides the conductor layers in a direction in a substrate surface; wherein a lower surface of the second portion is located below an upper surface of the first conductor layer, and an upper surface of the second portion is wider in a width in the direction, than the lower surface of the second portion and than the first portion.
    Type: Application
    Filed: February 13, 2024
    Publication date: August 15, 2024
    Applicant: Kioxia Corporation
    Inventors: Kohei DATE, Kenji AOYAMA, Keisuke SUDA, Minami TANAKA, Satoshi NAGASHIMA
  • Patent number: 11684072
    Abstract: A soy milk fermented substance is provided. The soy milk fermented substance has a taste and flavor or smooth physicality similar to that of yogurt obtained by fermenting milk with a lactic acid without applying processing treatment such as enzyme treatment or extraction treatment to soy milk which is a material and without adding a material such as a sugar source, even in a case where only Streptococcus thermophilus and Lactobacillus delbrueckii subsp. bulgaricus are employed as a lactic acid bacteria mixture starter at the time of making a fermented substance which employs soy milk as a material.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: June 27, 2023
    Assignee: KIKKOMAN CORPORATION
    Inventors: Daisuke Kaneko, Kenji Aoyama, Engels Wim, Wegkamp Arno, Kingma Fedde
  • Publication number: 20230104298
    Abstract: Provided are a fermented soy beverage concentrate and a novel method for producing the fermented soy beverage concentrate. Provided is a method for producing a fermented soy beverage concentrate, the method including: a fermentation step of fermenting a soy beverage by adding a microorganism to the soy beverage; a volume increase step of mixing a fermented soy beverage obtained in the fermentation step and a soy beverage together to achieve an increased volume, thereby giving a mixture having a pH of lower than 6.0; and a concentration step of concentrating a solid content from the mixture obtained in the volume increase step.
    Type: Application
    Filed: March 5, 2021
    Publication date: April 6, 2023
    Inventor: Kenji Aoyama
  • Patent number: 10784283
    Abstract: A semiconductor memory device includes a stacked body, a semiconductor member, a charge storage member, a first member, and second members. The stacked body includes electrode films arranged to be separated from each other along a first direction. A terrace is formed for each electrode film in an end portion of the stacked body in a second direction. The first member spreads along the first direction and the second direction. The first member is provided inside the cell portion. The second members are provided inside the end portion. The electrode film includes two portions separated from each other in a third direction. The two portions are separated in the third direction by the first member and the plurality of second members. An insulator between the electrode films is formed continuously between two sides of the plurality of second members in the third direction.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: September 22, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kenji Aoyama
  • Publication number: 20200105787
    Abstract: A semiconductor memory device includes a stacked body, a semiconductor member, a charge storage member, a first member, and second members. The stacked body includes electrode films arranged to be separated from each other along a first direction. A terrace is formed for each electrode film in an end portion of the stacked body in a second direction. The first member spreads along the first direction and the second direction. The first member is provided inside the cell portion. The second members are provided inside the end portion. The electrode film includes two portions separated from each other in a third direction. The two portions are separated in the third direction by the first member and the plurality of second members. An insulator between the electrode films is formed continuously between two sides of the plurality of second members in the third direction.
    Type: Application
    Filed: December 3, 2019
    Publication date: April 2, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Kenji AOYAMA
  • Patent number: 10553608
    Abstract: A semiconductor memory device includes a stacked body, a semiconductor member, a charge storage member, a first member, and second members. The stacked body includes electrode films arranged to be separated from each other along a first direction. A terrace is formed for each electrode film in an end portion of the stacked body in a second direction. The first member spreads along the first direction and the second direction. The first member is provided inside the cell portion. The second members are provided inside the end portion. The electrode film includes two portions separated from each other in a third direction. The two portions are separated in the third direction by the first member and the plurality of second members. An insulator between the electrode films is formed continuously between two sides of the plurality of second members in the third direction.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: February 4, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kenji Aoyama
  • Patent number: 10546871
    Abstract: A semiconductor memory device according to an embodiment comprises: a memory cell array region including a plurality of conductive layers that are electrically connected to a plurality of memory cells arranged in a first direction on a semiconductor substrate, the first direction intersecting a surface of the semiconductor substrate; a stepped part for contacting the plurality of conductive layers to a wiring line; a contact extending in the first direction and being connected to the conductive layer in the stepped part; and a plurality of columnar bodies extending in the first direction and penetrates the conductive layer in the stepped part and including a first columnar body having a first height and a second columnar body having a second height which is lower than the first height.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: January 28, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kenji Aoyama
  • Publication number: 20190267393
    Abstract: A semiconductor memory device includes a stacked body, a semiconductor member, a charge storage member, a first member, and second members. The stacked body includes electrode films arranged to be separated from each other along a first direction. A terrace is formed for each electrode film in an end portion of the stacked body in a second direction. The first member spreads along the first direction and the second direction. The first member is provided inside the cell portion. The second members are provided inside the end portion. The electrode film includes two portions separated from each other in a third direction. The two portions are separated in the third direction by the first member and the plurality of second members. An insulator between the electrode films is formed continuously between two sides of the plurality of second members in the third direction.
    Type: Application
    Filed: September 12, 2018
    Publication date: August 29, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Kenji AOYAMA
  • Patent number: 9929171
    Abstract: A semiconductor memory device according to an embodiment comprises: a semiconductor substrate; a semiconductor layer provided extending in a first direction above the semiconductor substrate, on the semiconductor substrate; a first insulating layer provided on a side surface of the semiconductor layer; a charge accumulation layer provided on a side surface of the first insulating layer; a block insulating layer provided on a side surface of the charge accumulation layer; and a plurality of conductive layers stacked in the first direction via an insulating layer, in a periphery of the block insulating layer. The block insulating layer includes: a first block insulating layer; and a second block insulating layer that has a permittivity which is higher than that of the first block insulating layer. A lower end of the second block insulating layer is positioned more upwardly than a lower end of the first insulating layer.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: March 27, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kenji Aoyama
  • Publication number: 20170278860
    Abstract: A semiconductor memory device according to an embodiment comprises: a memory cell array region including a plurality of conductive layers that are electrically connected to a plurality of memory cells arranged in a first direction on a semiconductor substrate, the first direction intersecting a surface of the semiconductor substrate; a stepped part for contacting the plurality of conductive layers to a wiring line; a contact extending in the first direction and being connected to the conductive layer in the stepped part; and a plurality of columnar bodies extending in the first direction and penetrates the conductive layer in the stepped part and including a first columnar body having a first height and a second columnar body having a second height which is lower than the first height.
    Type: Application
    Filed: September 12, 2016
    Publication date: September 28, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Kenji AOYAMA
  • Publication number: 20170263624
    Abstract: A semiconductor memory device according to an embodiment comprises: a semiconductor substrate; a semiconductor layer provided extending in a first direction above the semiconductor substrate, on the semiconductor substrate; a first insulating layer provided on a side surface of the semiconductor layer; a charge accumulation layer provided on a side surface of the first insulating layer; a block insulating layer provided on a side surface of the charge accumulation layer; and a plurality of conductive layers stacked in the first direction via an insulating layer, in a periphery of the block insulating layer. The block insulating layer includes: a first block insulating layer; and a second block insulating layer that has a permittivity which is higher than that of the first block insulating layer. A lower end of the second block insulating layer is positioned more upwardly than a lower end of the first insulating layer.
    Type: Application
    Filed: August 19, 2016
    Publication date: September 14, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kenji AOYAMA
  • Patent number: 9659957
    Abstract: According to one embodiment, a semiconductor memory device includes a first stacked body including a plurality of first electrode layers and a plurality of first insulating layers, the first electrode layers separately stacked each other, the first insulating layers provided between the first electrode layers; a second stacked body including a plurality of second electrode layers and a plurality of second insulating layers, the second electrode layers separately stacked each other, the second insulating layers provided between the second electrode layers, the second stacked body separated from the first stacked body in a first direction crossing a stacking direction of the first stacked body; and a first insulating portion provided between the first stacked body and the second stacked body, the first insulating portion provided integrally to the first insulating layers and the second insulating layers.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: May 23, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kenji Aoyama
  • Publication number: 20170062464
    Abstract: According to one embodiment, a semiconductor memory device includes a first stacked body including a plurality of first electrode layers and a plurality of first insulating layers, the first electrode layers separately stacked each other, the first insulating layers provided between the first electrode layers; a second stacked body including a plurality of second electrode layers and a plurality of second insulating layers, the second electrode layers separately stacked each other, the second insulating layers provided between the second electrode layers, the second stacked body separated from the first stacked body in a first direction crossing a stacking direction of the first stacked body; and a first insulating portion provided between the first stacked body and the second stacked body, the first insulating portion provided integrally to the first insulating layers and the second insulating layers.
    Type: Application
    Filed: February 18, 2016
    Publication date: March 2, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Kenji AOYAMA
  • Publication number: 20160268283
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode layers; a first electrode layer included in the plurality of electrode layers; a second electrode layer included in the plurality of electrode layers; a first insulating layer provided between the first electrode layer and the second electrode layer, and provided in contact with the first electrode layer and the second electrode layer; a semiconductor portion; a charge storage film; a first conductive film; and second conductive film. The first conductive film is provided between the first electrode layer and the charge storage film, and provided in contact with the first insulating layer. The second conductive film is provided between the second electrode layer and the charge storage film, and provided in contact with the first insulating layer.
    Type: Application
    Filed: July 9, 2015
    Publication date: September 15, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masayuki KITAMURA, Atsuko Sakata, Satoshi Wakatsuki, Takeshi Ishizaki, Daisuke Ikeno, Junichi Wada, Kei Watanabe, Shinya Okuda, Hirotaka Ogihara, Hiroshi Nakazawa, Tomonori Aoyama, Kenji Aoyama, Hideaki Aochi
  • Publication number: 20160268500
    Abstract: According to one embodiment, a resistance change memory includes first and second semiconductor pillars on a conductive region, a first word line including a first portion surrounding a side surface of the first pillar, a second portion surrounding a side surface of the second pillar, and a third portion connecting between the first and second portions, the first and second portions being physically separated from one another, a first resistance change element connected to an upper portion of the first semiconductor pillar, and a second resistance change element connected to an upper portion of the second semiconductor pillar.
    Type: Application
    Filed: August 26, 2015
    Publication date: September 15, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hironobu FURUHASHI, Kenji AOYAMA
  • Publication number: 20160268275
    Abstract: A non-volatile memory device includes a first semiconductor body extending in a first direction, an electrode extending in a second direction intersecting the first direction, a charge storage layer provided between the first semiconductor body and the electrode, and a first insulating layer provided between the electrode and the charge storage layer. The electrode includes a first layer, a second layer and a third layer. The first layer is provided on the first insulating layer and includes tungsten. The second layer is provided on the first layer and includes tungsten nitride. The third layer is provided on the second layer and includes tungsten.
    Type: Application
    Filed: August 27, 2015
    Publication date: September 15, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yuta WATANABE, Takeshi ISHIZAKI, Kana HIRAYAMA, Kenji AOYAMA
  • Publication number: 20160044931
    Abstract: [Problem to Be Solved] A present invention provides a soy milk fermented substance with a taste and flavor or smooth physicality similar to that of yogurt obtained by fermenting milk with a lactic acid without applying processing treatment such as enzyme treatment or extraction treatment to soy milk which is a material and without adding a material such as a sugar source, even in a case where only Streptococcus thermophilus and Lactobacillus delbrueckii subsp. bulgaricus are employed as a lactic acid bacteria mixture starter at the time of making a fermented substance which employs soy milk as a material. [Means for Solving the Problem] The problem is solved by a soy milk fermented substance obtained by using a lactic acid bacteria mixture starter including: Streptococcus thermophilus which is capable of accumulating 0.4 g/L or more of fructose in the fermented substance when inoculated and cultured in soy milk; and Lactobacillus debrueckii subsp. bulgaricus which is capable of accumulating 0.
    Type: Application
    Filed: April 2, 2014
    Publication date: February 18, 2016
    Applicant: KIKKOMAN CORPORATION
    Inventors: Daisuke KANEKO, Kenji AOYAMA, Engels WIM, Wegkamp ARNO, Kingma FEDDE
  • Publication number: 20160013128
    Abstract: A method for manufacturing a semiconductor device includes forming a metal-containing layer over a semiconductor substrate, forming an insulating film to cover the semiconductor substrate and the metal-containing layer, forming a first contact hole that penetrates through the insulating film to reach the semiconductor substrate, forming a second contact hole that penetrates through the insulating film to reach the metal-containing layer, forming a first conductive plug on a portion, exposed through the first contact hole, of the semiconductor substrate and including a first material, forming a second conductive plug on the first conductive plug and including a second material, the semiconductor substrate being closer to a lower surface of the second conductive plug than to an upper surface of the metal-containing layer, and forming a third conductive plug on a portion, exposed through the second contact hole, of the metal-containing layer, the third conductive plug including a third material.
    Type: Application
    Filed: January 29, 2015
    Publication date: January 14, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenji AOYAMA, Hideki Inokuma, Kana Hirayama