Abstract: A refrigeration cycle device comprises a refrigerant, a compressor that compresses the refrigerant, and a refrigerating machine oil that lubricates a sliding part of the compressor. The refrigerant includes trifluoroiodomethane. The refrigerating machine oil includes a base oil and a quinone additive. The quinone additive is at least one selected from the group consisting of 1,4-benzoquinone, 1,2-benzoquinone, 2-methyl-1,4-benzoquinone, 2-phenyl-1,4-benzoquinone, 2-tert-butyl-1,4-benzoquinone, 1,4-naphthoquinone, 1,2-naphthoquinone, 2,6-naphthoquinone, 2-hydroxy-1,4-naphthoquinone, and 1,4-anthraquinone.

Abstract: A silicon carbide epitaxial substrate includes: a silicon carbide single crystal substrate; a first silicon carbide layer on the silicon carbide single crystal substrate, the first silicon carbide layer having a first concentration of carriers; and a second silicon carbide layer on the first silicon carbide layer, the second silicon carbide layer having a second concentration of carriers. A transition region in which the concentration of the carriers is changed between the first concentration and the second concentration has a width of less than or equal to 1 ?m. A ratio of a standard deviation of the second concentration to an average value of the second concentration is less than or equal to 5%, the ratio being defined as uniformity of the second concentration in a central region. The central region has an arithmetic mean roughness of less than or equal to 0.5 nm.

Abstract: A silicon carbide epitaxial substrate includes: a silicon carbide single crystal substrate; and an epitaxial layer. The silicon carbide single crystal substrate has a diameter of not less than 100 mm. The epitaxial layer has a thickness of not less than 10 ?m. The epitaxial layer has a carrier concentration of not less than 1×1014 cm?3 and not more than 1×1016 cm?3. A ratio of a standard deviation of the carrier concentration in a plane of the epitaxial layer to an average value of the carrier concentration in the plane is not more than 10%. The epitaxial layer has a main surface. The main surface has an arithmetic mean roughness Sa of not more than 0.3 nm. An area density of pits originated from a threading screw dislocation is not more than 1000 cm?2. Each of the pits has a maximum depth of not less than 8 nm.

Abstract: A trench having an opening and a corner portion is formed in a silicon carbide substrate. A corner insulating film is formed to cover the corner portion. A gate insulating film is formed to cover a region extending from the opening to the corner portion. The step of forming the gate insulating film includes a step of thermally oxidizing the trench provided with the corner insulating film. The step of thermally oxidizing the trench includes a step of heating the silicon carbide substrate at not less than 1300° C. Accordingly, sufficient insulation reliability of the gate insulating film is secured near the opening of the trench while preventing dielectric breakdown of the gate oxide film at the bottom portion of the trench.

Abstract: The silicon carbide layer includes a second main surface opposite to a surface in contact with the silicon carbide single crystal substrate. The second main surface corresponds to a plane inclined relative to a {0001} plane in an off direction. The second main surface has a maximum diameter of not less than 100 mm. The second main surface has an outer circumferential region and a central region, the central region being surrounded by the outer circumferential region. The central region is provided with a first dislocation array of first half loops along a straight line perpendicular to the off direction. Each of the first half loops includes a pair of threading edge dislocations exposed at the second main surface. An area density of the first dislocation array at the central region is not more than 10/cm2.

Abstract: A silicon carbide substrate has first to third semiconductor layers. The first and third semiconductor layers have a first conductivity type, and the second semiconductor layer has a second conductivity type. A trench has a bottom surface and first to third side surfaces, the bottom surface being constituted of the first semiconductor layer, the first to third side surfaces being respectively constituted of the first to third semiconductor layers. A gate insulating film having a bottom portion and a side wall portion is provided on the trench. The bottom portion has a minimum thickness d0. A portion of the side wall portion on the second side surface has a minimum thickness d1. A portion, connected to the bottom portion, of the side wall portion on the first side surface has a thickness d2. Moreover, d2>d1 and d2>d0 are satisfied.

Abstract: A silicon carbide substrate has first to third semiconductor layers. The first and third semiconductor layers have a first conductivity type, and the second semiconductor layer has a second conductivity type. A trench has a bottom surface and first to third side surfaces, the bottom surface being constituted of the first semiconductor layer, the first to third side surfaces being respectively constituted of the first to third semiconductor layers. A gate insulating film having a bottom portion and a side wall portion is provided on the trench. The bottom portion has a minimum thickness d0. A portion of the side wall portion on the second side surface has a minimum thickness d1. A portion, connected to the bottom portion, of the side wall portion on the first side surface has a thickness d2. Moreover, d2>d1 and d2>d0 are satisfied.

Abstract: A silicon carbide substrate has first to third semiconductor layers. The first and third semiconductor layers have a first conductivity type, and the second semiconductor layer has a second conductivity type. A trench has a bottom surface and first to third side surfaces, the bottom surface being constituted of the first semiconductor layer, the first to third side surfaces being respectively constituted of the first to third semiconductor layers. A gate insulating film having a bottom portion and a side wall portion is provided on the trench. The bottom portion has a minimum thickness d0. A portion of the side wall portion on the second side surface has a minimum thickness d1. A portion, connected to the bottom portion, of the side wall portion on the first side surface has a thickness d2. Moreover, d2>d1 and d2>d0 are satisfied.

Abstract: A trench having an opening and a corner portion is formed in a silicon carbide substrate. A corner insulating film is formed to cover the corner portion. A gate insulating film is formed to cover a region extending from the opening to the corner portion. The step of forming the gate insulating film includes a step of thermally oxidizing the trench provided with the corner insulating film. The step of thermally oxidizing the trench includes a step of heating the silicon carbide substrate at not less than 1300° C. Accordingly, sufficient insulation reliability of the gate insulating film is secured near the opening of the trench while preventing dielectric breakdown of the gate oxide film at the bottom portion of the trench.

Abstract: A semiconductor optical integrated device includes a substrate having a main surface with a first and second regions arranged along a waveguiding direction; a gain region including a first cladding layer, an active layer, and a second cladding layer arranged on the first region of the main surface; and a wavelength control region including a third cladding layer, an optical waveguide layer, and a fourth cladding layer arranged on the second region of the main surface and including a heater arranged along the optical waveguide layer. The substrate includes a through hole extending from a back surface of the substrate in the thickness direction and reaching the first region. A metal member is arranged in the through hole. The metal member extends from the back surface of the substrate in the thickness direction and is in contact with the first cladding layer.

Abstract: A method for manufacturing a semiconductor optical device includes the steps of growing a stacked semiconductor layer on a substrate having a cleavage direction in a first direction; forming a first mask having a plurality of openings arranged in the first direction; forming a mark array by etching the stacked semiconductor layer using the first mask; forming a second mask having first and second openings extending in a second direction intersecting the first direction; obtaining a substrate product by forming first and second grooves, and a waveguide mesa by etching the stacked semiconductor layer by using the second mask; and producing a laser diode bar by cleaving the substrate product including the waveguide mesa. First and second residual marks are formed on the upper surface of the waveguide mesa. First and second transfer marks are formed on the bottoms of the first and the second grooves, respectively.

Abstract: A silicon carbide substrate is prepared which has a main surface covered with a silicon dioxide layer. In the silicon dioxide layer, an opening is formed by etching. In the opening, a residue resulting from the etching is on the silicon carbide substrate. The residue is removed by plasma etching in which only an inert gas is introduced. After removing the residue, under heating, a reactive gas is supplied to the silicon carbide substrate covered with the silicon dioxide layer having the opening formed therein. In this way, a trench is formed in the main surface of the silicon carbide substrate.

Abstract: A measuring device includes: a probe applying a voltage to an electrode of an element; and a supplying member supplying an insulating liquid to a contact portion between the electrode and the probe via a surface of the probe. Accordingly, the insulating liquid can be securely supplied to the contact portion between the electrode and the probe via the surface of the probe positioned relative to the electrode.

Abstract: A silicon carbide substrate is prepared which has a main surface covered with a silicon dioxide layer. In the silicon dioxide layer, an opening is formed by etching. In the opening, a residue resulting from the etching is on the silicon carbide substrate. The residue is removed by plasma etching in which only an inert gas is introduced. After removing the residue, under heating, a reactive gas is supplied to the silicon carbide substrate covered with the silicon dioxide layer having the opening formed therein. In this way, a trench is formed in the main surface of the silicon carbide substrate.

Abstract: A method for producing an integrated optical device includes the steps of growing, on a substrate including first and second regions, a first stacked semiconductor layer, a first cladding layer, and a side-etching layer; etching the first stacked semiconductor layer through a first etching mask formed on the first region; selectively growing, on the second region, a second stacked semiconductor layer and a second cladding layer; growing a third cladding layer and a contact layer on the first and second stacked semiconductor layers; and forming a ridge structure. The step of etching the first stacked semiconductor layer includes a step of forming an overhang between the first cladding layer and the first etching mask. The step of forming a ridge structure includes first, second, and third wet-etching steps in which the third cladding layer, the side-etching layer and the first and second cladding layers are selectively etched, respectively.

Abstract: A method for producing a semiconductor optical integrated device includes the steps of forming a substrate product including first and second stacked semiconductor layer portions; forming a first mask on the first and second stacked semiconductor layer portions, the first mask including a stripe-shaped first pattern region and a second pattern region, the second pattern region including a first end edge; forming a stripe-shaped mesa structure; removing the second pattern region of the first mask; forming a second mask on the second stacked semiconductor layer portion; and selectively growing a buried semiconductor layer with the first and second masks. The second mask includes a second end edge separated from the first end edge of the first mask, the second end edge being located on the side of the second stacked semiconductor layer portion in the predetermined direction with respect to the first end edge of the first mask.

Abstract: A first layer of a first conductivity type made of silicon carbide is formed. A second layer of a second conductivity type different from the first conductivity type positioned on the first layer, and a third layer of the first conductivity type positioned on the second layer are formed. The step of forming second and third layers includes the steps of performing impurity ion implantation, and performing heat treatment for activating impurities implanted by the impurity ion implantation. After the step of performing heat treatment, a trench having a side wall penetrating the third layer and the second layer and having a bottom reaching the first layer is formed. A gate insulating film to cover the side wall of the trench is formed. As a result, a silicon carbide semiconductor device having a low ON resistance is provided.

Abstract: A method for producing a semiconductor optical device includes a first etching step of etching a stacked semiconductor layer with a first mask to form a stripe-shaped optical waveguide, the stripe-shaped optical waveguide including first and second stripe-shaped optical waveguides formed on first and second regions of a substrate, respectively; a step of forming a second mask on the stacked semiconductor layer with the first mask left; and a second etching step of etching the stacked semiconductor layer on the first region with the first and second masks. The second mask has a pattern for forming a mesa structure and includes an opening including first and second opening edges remote from side surfaces of the first stripe-shaped optical waveguide. The mesa structure is formed of the first stripe-shaped optical waveguide in the second etching step. The second stripe-shaped optical waveguide formed in the first etching step has a ridge structure.

Abstract: A method of making a semiconductor optical integrated device includes the steps of forming, on a substrate, a plurality of semiconductor integrated devices including a first optical semiconductor element having a first bonding pad and a second optical semiconductor element; forming a plurality of bar-shaped semiconductor optical integrated device arrays by cutting the substrate, each of the semiconductor optical integrated device arrays including two or more semiconductor optical integrated devices; alternately arranging the plurality of semiconductor optical integrated device arrays and a plurality of spacers in a thickness direction of the substrate so as to be fixed in place; and forming a coating film on a facet of the semiconductor optical integrated device array. Furthermore, the spacer has a movable portion facing the first bonding pad, the movable portion protruding toward the first bonding pad and being displaceable in a protruding direction.

Abstract: A method for producing a semiconductor optical device, includes the steps of: (a) forming a semiconductor region on a substrate, the substrate including first and second areas; the first area including device sections (b) forming a first mask on the semiconductor region, the first mask including first patterns periodically arranged in the first area and a second pattern provided in the second area; (c) forming a plurality of periodic structures in each of the device sections and a monitoring structure in the second area by using the first mask, the periodic structures respectively corresponding to the first patterns, the monitoring structure corresponding to the second pattern; (d) measuring a shape of the monitoring structure; (e) selecting a desired periodic structure from the plurality of periodic structures on a basis of a result of measuring the shape of the monitoring structure; (f) forming a second mask including a pattern on the desired periodic structure; and (g) forming stripe mesas including the de