Patents by Inventor Kenji Kouno

Kenji Kouno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220362985
    Abstract: To provide a method for producing a multilayered container, which has a layer containing a polyester resin as a main component and a layer containing a polyamide resin as a main component and in which delamination is less likely to occur. The method for producing a multilayered container contains biaxially stretching and blow molding a preform having a polyester resin layer and a polyamide resin layer; a storage elastic modulus G? of the polyamide resin being 5 MPa or more and less than 100 MPa; a moisture content of the polyamide resin layer being 0.5% or less; and the polyamide resin containing a xylylenediamine-based polyamide resin, 70 mol % or more of the structural units derived from diamine being derived from meta-xylylenediamine, from 80 to 97 mol % of the structural units derived from dicarboxylic acid being derived from an am-straight chain aliphatic dicarboxylic acid having from 4 to 8 carbons and from 20 to 3 mol % being derived from aromatic dicarboxylic acid.
    Type: Application
    Filed: September 25, 2020
    Publication date: November 17, 2022
    Inventors: Masaki YAMANAKA, Kenji KOUNO, Takanori MIYABE
  • Publication number: 20220190155
    Abstract: A semiconductor device includes a source electrode, a drain electrode and a gate. The gate controls a current flowing between the source electrode and the drain electrode. Capacitance between the gate and the drain electrode is first capacitance. Capacitance between the gate and the source electrode is second capacitance. A sum of the first capacitance and the second capacitance is equal to third capacitance. Total switching loss is a sum of first switching loss and second switching loss. The first switching loss is defined by a current variation rate, and the second switching loss is defined by a voltage variation rate. A capacitance ratio of the first capacitance to the third capacitance is set to a ratio to satisfying a relationship that the total switching loss is smaller than a predetermined value.
    Type: Application
    Filed: March 7, 2022
    Publication date: June 16, 2022
    Inventor: Kenji KOUNO
  • Publication number: 20220140121
    Abstract: A plug electrode is subject to etch back to remain in a contact hole and expose a barrier metal on a top surface of an interlayer insulating film. The barrier metal is subject to etch back, exposing the top surface of the interlayer insulating film. Remaining element structures are formed. After lifetime is controlled by irradiation of helium or an electron beam, hydrogen annealing is performed. During the hydrogen annealing, the barrier metal is not present on the interlayer insulating film covering a gate electrode, enabling hydrogen atoms to reach a mesa part, whereby lattice defects generated in the mesa part by the irradiation of helium or an electron beam are recovered, recovering the gate threshold voltage. Thus, predetermined characteristics of a semiconductor device having a structure where a plug electrode is provided in a contact hole, via barrier metal are easily and stably obtained when lifetime control is performed.
    Type: Application
    Filed: January 19, 2022
    Publication date: May 5, 2022
    Applicants: FUJI ELECTRIC CO., LTD., DENSO CORPORATION
    Inventors: Hiroshi MIYATA, Seiji NOGUCHI, Souichi YOSHIDA, Hiromitsu TANABE, Kenji KOUNO, Yasushi OKURA
  • Patent number: 11264490
    Abstract: A plug electrode is subject to etch back to remain in a contact hole and expose a barrier metal on a top surface of an interlayer insulating film. The barrier metal is subject to etch back, exposing the top surface of the interlayer insulating film. Remaining element structures are formed. After lifetime is controlled by irradiation of helium or an electron beam, hydrogen annealing is performed. During the hydrogen annealing, the barrier metal is not present on the interlayer insulating film covering a gate electrode, enabling hydrogen atoms to reach a mesa part, whereby lattice defects generated in the mesa part by the irradiation of helium or an electron beam are recovered, recovering the gate threshold voltage. Thus, predetermined characteristics of a semiconductor device having a structure where a plug electrode is provided in a contact hole, via barrier metal are easily and stably obtained when lifetime control is performed.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: March 1, 2022
    Assignees: FUJI ELECTRIC CO., LTD., DENSO CORPORATION
    Inventors: Hiroshi Miyata, Seiji Noguchi, Souichi Yoshida, Hiromitsu Tanabe, Kenji Kouno, Yasushi Okura
  • Patent number: 11111365
    Abstract: A polyolefin-based structure includes 60 to 97% by mass of a polyolefin (A), 1 to 35% by mass of an acid-modified polyolefin (B), and 2 to 35% by mass of a polyamide resin (C), in which the polyamide resin (C) is dispersed in a layered form in the polyolefin (A), and the polyamide resin (C) is a melt-kneaded product of 30 to 70% by mass of a polyamide (X) that contains a diamine unit containing 70 mol % or more of a m-xylylenediamine unit and a dicarboxylic acid unit containing an ?,?-linear aliphatic dicarboxylic acid unit and 30 to 70% by mass of an aliphatic polyamide (Y) (provided that a total of the polyamide (X) and the polyamide (Y) is taken as 100% by mass), and a difference between a melting point Tm0 of the polyamide (X) as observed by differential scanning calorimetry and a melting point Tm1 derived from the polyamide (X) in the polyamide resin (C), is 0.1 to 2.5° C.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: September 7, 2021
    Assignee: Mitsubishi Gas Chemical Company, Inc.
    Inventors: Tomonori Kato, Kenji Kouno
  • Patent number: 10714715
    Abstract: An electric storage device includes an electrode assembly, a case that includes a defining wall and houses the electrode assembly, a sealing member that is arranged on the defining wall, and a conductive member that is electrically connected to the electrode assembly, the conductive member being supported by the sealing member. At least a portion of the defining wall where the sealing member is arranged includes an aluminum-based metallic material. The sealing member includes a material that is softer than the material for the at least a portion of the defining wall where the sealing member is arranged. The sealing member includes polyphenylene sulfide (PPS) resin and an elastomer. The elastomer is contained in an amount of 2% to 20% by weight. The conductive member is crimped in such a manner that the sealing member is pressed against the defining wall.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: July 14, 2020
    Assignee: GS YUASA INTERNATIONAL LTD.
    Inventors: Masakazu Tsutsumi, Hajime Kawamoto, Katsuhiko Okamoto, Shinsuke Yoshitake, Takuma Tonari, Jun Nakamura, Kenji Kouno
  • Publication number: 20200212546
    Abstract: The wearable antenna device includes an antenna part—attached to a part of a garment including a body accommodation part—that accommodates a part of a body, and a functional element arranged in a position of the garment in such a way that at least a part of the functional element is opposed to the antenna part with the body accommodation part interposed therebetween.
    Type: Application
    Filed: April 10, 2018
    Publication date: July 2, 2020
    Applicants: NEC CORPORATION, NEC PLATFORMS, LTD.
    Inventors: Shinichirou KODAMA, Kenji KOUNO, Tomohiro SHIMODA, Kazuaki MUROFUSHI, Hidenori MORIYA, Mitsuno KONDO, Sumio HIRAKU, yUKIO ANDO, Tetsuya NAGATA
  • Patent number: 10658360
    Abstract: On a front surface side of an n? semiconductor substrate, an emitter electrode and trench gates each including a p base layer, a trench, a gate oxide film and a gate electrode are provided in an IGBT region and a FWD region. Among p base layers each between adjacent trenches, p base layers having an n+ emitter region are the IGBT emitter region and the p base layers not having the n+ emitter region are the FWD anode region. A lateral width of an n+ cathode region is narrower than a lateral width of the FWD anode region. A difference of a lateral width of the FWD anode region and a lateral width of the n+ cathode region is 50 ?m or more. Thus, a semiconductor device may be provided that reduces the forward voltage drop while suppressing waveform oscillation during reverse recovery and having soft recover characteristics.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: May 19, 2020
    Assignees: FUJI ELECTRIC CO., LTD., DENSO CORPORATION
    Inventors: Souichi Yoshida, Masaki Tamura, Kenji Kouno, Hiromitsu Tanabe
  • Patent number: 10629678
    Abstract: A method of manufacturing a semiconductor device having an insulated gate bipolar transistor portion and a freewheeling diode portion. The method includes introducing an impurity to a rear surface of a semiconductor substrate, performing first heat treating to activate the impurity to form a field stop layer, performing a first irradiation to irradiate light ions from the rear surface of semiconductor substrate to form, in the semiconductor substrate, a first low-lifetime region, performing a second irradiation to irradiate the light ions from the rear surface of the semiconductor substrate to form, in the field stop layer, a second low-lifetime region, and performing second heat treating to reduce a density of defects generated in the field stop layer when the second irradiation is performed. Each of the first and second low-lifetime regions has a carrier lifetime thereof shorter than that of any region of the semiconductor device other than the first and second low-lifetime regions.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: April 21, 2020
    Assignees: FUJI ELECTRIC CO., LTD., DENSO CORPORATION
    Inventors: Souichi Yoshida, Seiji Noguchi, Kenji Kouno, Hiromitsu Tanabe
  • Patent number: 10580853
    Abstract: A method of manufacturing a semiconductor device having an insulated gate bipolar transistor portion and a freewheeling diode portion. The method includes introducing an impurity to a rear surface of a semiconductor substrate, performing first heat treating to activate the impurity to form a field stop layer, performing a first irradiation to irradiate light ions from the rear surface of semiconductor substrate to form, in the semiconductor substrate, a first low-lifetime region, performing a second irradiation to irradiate the light ions from the rear surface of the semiconductor substrate to form, in the field stop layer, a second low-lifetime region, and performing second heat treating to reduce a density of defects generated in the field stop layer when the second irradiation is performed. Each of the first and second low-lifetime regions has a carrier lifetime thereof shorter than that of any region of the semiconductor device other than the first and second low-lifetime regions.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: March 3, 2020
    Assignees: FUJI ELECTRIC CO., LTD., DENSO CORPORATION
    Inventors: Souichi Yoshida, Seiji Noguchi, Kenji Kouno, Hiromitsu Tanabe
  • Publication number: 20200048441
    Abstract: A polyolefin-based structure includes 60 to 97% by mass of a polyolefin (A), 1 to 35% by mass of an acid-modified polyolefin (B), and 2 to 35% by mass of a polyamide resin (C), in which the polyamide resin (C) is dispersed in a layered form in the polyolefin (A), and the polyamide resin (C) is a melt-kneaded product of 30 to 70% by mass of a polyamide (X) that contains a diamine unit containing 70 mol % or more of a m-xylylenediamine unit and a dicarboxylic acid unit containing an ?,?-linear aliphatic dicarboxylic acid unit and 30 to 70% by mass of an aliphatic polyamide (Y) (provided that a total of the polyamide (X) and the polyamide (Y) is taken as 100% by mass), and a difference between a melting point Tm0 of the polyamide (X) as observed by differential scanning calorimetry and a melting point Tm1 derived from the polyamide (X) in the polyamide resin (C), is 0.1 to 2.5° C.
    Type: Application
    Filed: September 19, 2017
    Publication date: February 13, 2020
    Inventors: Tomonori KATO, Kenji KOUNO
  • Patent number: 10543961
    Abstract: A container cap is a container cap including a molded article formed of a resin composition containing 70 to 94% by mass of a polyolefin (A), 3 to 15% by mass of an acid-modified polyolefin (B) and 3 to 15% by mass of a m-xylylene group-containing polyamide (C), in which a ratio (X/Y) of a percentage (X) of polyamide-derived nitrogen in a cap top surface portion to a percentage (Y) of polyamide-derived nitrogen in a cap side surface portion, is 1.2 to 3.0, as measured by a total nitrogen analysis.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: January 28, 2020
    Assignee: Mitsubishi Gas Chemical Company, Inc.
    Inventors: Tomonori Kato, Kenji Kouno
  • Publication number: 20190256256
    Abstract: A container cap is a container cap including a molded article formed of a resin composition containing 70 to 94% by mass of a polyolefin (A), 3 to 15% by mass of an acid-modified polyolefin (B) and 3 to 15% by mass of a m-xylylene group-containing polyamide (C), in which a ratio (X/Y) of a percentage (X) of polyamide-derived nitrogen in a cap top surface portion to a percentage (Y) of polyamide-derived nitrogen in a cap side surface portion, is 1.2 to 3.0, as measured by a total nitrogen analysis.
    Type: Application
    Filed: September 8, 2017
    Publication date: August 22, 2019
    Inventors: Tomonori KATO, Kenji KOUNO
  • Patent number: 10300648
    Abstract: The production method for a polyolefin-based structure of the present invention produces a polyolefin-based structure from a mixed source material containing a polyolefin (A), an acid-modified polyolefin (B) and a gas barrier resin (C) using a molding machine 10, under the condition mentioned below. The molding machine 10 is equipped with a single-screw extruder 11, a die head 12, and an adaptor 13 for feeding the mixed source material from the single-screw extruder 11 to the die head 12. Am+10° C.?T1?Cm?10° C. (1), Cm?30° C.?T2?Cm+30° C. (2), Cm?10° C.?T3?Cm+50° C. (3), Cm?30° C.?T4?Cm+30° C. (4). T1 is a cylinder temperature in a section corresponding to a supply zone 21A and a compression zone 21B, T2 is a cylinder temperature in a section corresponding to a metering zone 21C, T3 is a temperature of an adaptor 13, T4 is a temperature of a die head, Am is the melting point of the component (A), and Cm is the melting point of the component (C).
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: May 28, 2019
    Assignee: Mitsubishi Gas Chemical Company, Inc.
    Inventors: Kentaro Ishii, Tomonori Kato, Jun Mitadera, Kenji Kouno
  • Patent number: 10256234
    Abstract: A semiconductor device includes a semiconductor substrate provided with an IGBT cell having a collector region and a diode cell having a cathode region, a first defect layer and a second defect layer in a drift region. A region present in the drift region and surrounded by an interface between the IGBT cell and the diode cell orthogonal to a first principal plane, and a plane passing through a boundary between the collector region and the cathode region on a boundary line along an interface between the collector region and the drift region and crossing the first principal plane at an angle of 45 degrees is referred to as a boundary region. The diode cell satisfies a relationship of SD1>S, in which S is an area occupied by the boundary region and SD1 is an area occupied by the diode cell in a surface of the drift region.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: April 9, 2019
    Assignee: DENSO CORPORATION
    Inventors: Hiromitsu Tanabe, Kenji Kouno
  • Patent number: 10256212
    Abstract: The present disclosure provides a semiconductor chip. The semiconductor chip includes a switching element having a gate electrode, a first pad, and a second pad. The first control pad is electrically connected to the gate electrode and applied with a voltage controlling the switching element to switch on or switch off. The second control pad provides a current path of a control current flowing between the first control pad and the second control pad when the switching element is in a switch-on state. One of the first control pad or the second control pad includes two pad components and a remaining one of the first control pad or the second control pad is disposed between the two pad components of the one of the first control pad or the second control pad.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: April 9, 2019
    Assignee: DENSO CORPORATION
    Inventors: Kenji Kouno, Hiromitsu Tanabe
  • Publication number: 20190097030
    Abstract: A plug electrode is subject to etch back to remain in a contact hole and expose a barrier metal on a top surface of an interlayer insulating film. The barrier metal is subject to etch back, exposing the top surface of the interlayer insulating film. Remaining element structures are formed. After lifetime is controlled by irradiation of helium or an electron beam, hydrogen annealing is performed. During the hydrogen annealing, the barrier metal is not present on the interlayer insulating film covering a gate electrode, enabling hydrogen atoms to reach a mesa part, whereby lattice defects generated in the mesa part by the irradiation of helium or an electron beam are recovered, recovering the gate threshold voltage. Thus, predetermined characteristics of a semiconductor device having a structure where a plug electrode is provided in a contact hole, via barrier metal are easily and stably obtained when lifetime control is performed.
    Type: Application
    Filed: November 29, 2018
    Publication date: March 28, 2019
    Applicants: FUJI ELECTRIC CO., LTD., DENSO CORPORATION
    Inventors: Hiroshi Miyata, Seiji Noguchi, Souichi Yoshida, Hiromitsu Tanabe, Kenji Kouno, Yasushi Okura
  • Patent number: 10170607
    Abstract: A semiconductor device has a semiconductor substrate including a first conductivity-type drift layer, a second conductivity-type base layer disposed in a surface layer portion of the drift layer, and a second conductivity-type collector layer and a first conductivity-type cathode layer disposed opposite to the base layer with respect to the drift layer. In the semiconductor substrate, an IGBT region and a diode region are alternately and repetitively arranged. The IGBT region and the diode region are divided by a boundary between the collector layer and the cathode layer. The collector layer is defined as a first collector layer. The semiconductor device includes a second collector layer having a second conductivity-type impurity concentration higher than that of the first collector layer, at a surface of the semiconductor substrate adjacent to the first collector layer and the cathode layer.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: January 1, 2019
    Assignee: DENSO CORPORATION
    Inventor: Kenji Kouno
  • Publication number: 20180294250
    Abstract: The present disclosure provides a semiconductor chip. The semiconductor chip includes a switching element having a gate electrode, a first pad, and a second pad. The first control pad is electrically connected to the gate electrode and applied with a voltage controlling the switching element to switch on or switch off. The second control pad provides a current path of a control current flowing between the first control pad and the second control pad when the switching element is in a switch-on state. One of the first control pad or the second control pad includes two pad components and a remaining one of the first control pad or the second control pad is disposed between the two pad components of the one of the first control pad or the second control pad.
    Type: Application
    Filed: May 27, 2016
    Publication date: October 11, 2018
    Inventors: Kenji KOUNO, Hiromitsu TANABE
  • Patent number: 10062753
    Abstract: A semiconductor device includes a semiconductor substrate having a drift layer, a base layer, a collector layer and a cathode layer. The semiconductor substrate includes a cell region and an outer peripheral region surrounding the cell region. The cell region includes an IGBT region and a diode region. The semiconductor substrate further includes a damage region arranged in the diode region and a part of the outer peripheral region adjacent to a boundary between the outer peripheral region and the diode region. A length, in a longitudinal direction of the diode region, of the part of the outer peripheral region, in which the damage region is arranged, is equal to or more than twice of a thickness of the semiconductor substrate. As a result, recovery characteristic is improved in a portion of the diode region adjacent to the boundary between the outer peripheral region and the diode region.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: August 28, 2018
    Assignee: DENSO CORPORATION
    Inventor: Kenji Kouno