Patents by Inventor Kenji Nishikawa
Kenji Nishikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170309547Abstract: A method for manufacturing a semiconductor device includes preparing a lead frame that includes a die pad including a first plane and a second plane located on an opposite side of the first plane, and a plurality of leads arranged next to the die pad, mounting a semiconductor chip including a surface, a plurality of electrodes formed over the surface, and a reverse side located on an opposite side of the surface over a chip mounting area of the first plane of the die pad, electrically coupling parts of the electrodes of the semiconductor chip and the leads through a plurality of first wires and electrically coupling other parts of the electrodes and the die pad through a second wire after the mounting the semiconductor chip, and after the electrically coupling, sealing the semiconductor chip, the first wires, and the second wire with a resin.Type: ApplicationFiled: July 7, 2017Publication date: October 26, 2017Inventors: Akito SHIMIZU, Kenji Nishikawa, Sadayuki Moroi, Tomoo Imura
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Patent number: 9741641Abstract: A semiconductor device, includes a die pad that has a first main surface and a second main surface located on the opposite side of the first main surface; a lead arranged next to the die pad; a semiconductor chip that has a surface, a first electrode and a second electrode formed on the surface, and a reverse side located on the opposite side of the surface, and is mounted on a chip mounting area of the first main of the die pad; a first wire that electrically couples the first electrode of the semiconductor chip and the lead; a second wire that electrically couples the second electrode of the semiconductor chip and the die pad; and a sealed body that seals the semiconductor chip, the first wire, and the second wire.Type: GrantFiled: January 16, 2016Date of Patent: August 22, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Akito Shimizu, Kenji Nishikawa, Sadayuki Moroi, Tomoo Imura
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Patent number: 9698480Abstract: A first base radiation element has a first end connected to the feed point, and a second end. A second base radiation element has a first end connected to the ground point, and a second end. The first and second base radiation elements respectively include portions extending in a first direction and close to each other. The first base radiation element is branched into first and second branch radiation elements at a first branch point located at the second end of the first base radiation element, the first branch radiation element includes a portion extending in the first direction, and the second branch radiation element includes a portion extending in a second direction opposite to the first direction. The end of the second base radiation element is connected to a connecting point different from the first branch point of the first branch radiation element.Type: GrantFiled: March 6, 2013Date of Patent: July 4, 2017Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Kazuya Tani, Toshiharu Ishimura, Kenji Nishikawa, Kazuya Nakano
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Publication number: 20170158663Abstract: The invention provides a novel ?-halogen-substituted thiophene compound salt that has a potent LPA receptor antagonistic action and is useful as a medicament. The salt is represented by the general formula (I): (wherein R is a hydrogen atom or a methoxy group; X is a halogen atom; A is selected from the group consisting of: ;M is an alkali metal or an alkaline earth metal; and n is 1 when M is an alkali metal and is 2 when M is an alkaline earth metal).Type: ApplicationFiled: June 26, 2015Publication date: June 8, 2017Applicant: UBE INDUSTRIES, LTD.Inventors: Noriaki IWASE, Hiroshi NISHIDA, Makoto OKUDO, Masaaki ITO, Shigeyuki KONO, Masaaki MATOYAMA, Shigeru USHIYAMA, Eiji OKANARI, Hirofumi MATSUNAGA, Kenji NISHIKAWA, Tomio KIMURA
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Patent number: 9604298Abstract: The removal starting position (8S1) of a first removal process and the four removal starting positions (8S21-8S24) in a second removal process are established on an imaginary circle (7I) with a prescribed radius (R) that is inscribed in the apex (7C) of an incomplete thread part (7a). In each removal process, the tip of the screw thread cutting tool shaves off the apex (7C) of the incomplete thread part (7a) into respective recesses, contacting the imaginary inscribed circle (7I) from the outside (above). The multiple cutting surfaces of the apex (7C) are formed in parallel helices (that is, as mutually adjacent helical recesses) from the starting position to the ending position of the incomplete thread part. Points and burrs in the incomplete thread part can thereby be eliminated or reduced without loss of the ability to screw together with a partner threaded fastener (threaded portion).Type: GrantFiled: July 27, 2012Date of Patent: March 28, 2017Assignee: RICOH ELEMEX CORPORATIONInventors: Toshiyuki Shimizu, Masao Kobayashi, Kenji Nishikawa, Seiji Otani, Takaya Nishikawa, Manabu Takeda
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Patent number: 9601221Abstract: An opening and closing device that opens and closes an access port opened from a substantially cylindrical working platform disposed inside a reactor vessel and used to access a nozzle stub of the reactor vessel from the inside of the working platform, the opening and closing device includes: a cover that is slidable along an outer peripheral surface or an inner peripheral surface of the working platform from a closing position where the access port is closed to an opening position where the access port is opened; and moving device for sliding the cover.Type: GrantFiled: June 8, 2010Date of Patent: March 21, 2017Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.Inventors: Atsushi Sugiura, Takumi Hori, Kenji Nishikawa, Ken Onishi, Noriaki Shimonabe, Satoshi Tsuzuki, Ikuo Wakamoto
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Patent number: 9524803Abstract: A reactor vessel that performs work inside a nozzle stub of the reactor vessel, including a platform unit that is provided at an upper portion inside the reactor vessel and includes a substantially cylindrical side wall portion and a bottom portion blocking the lower end of the side wall portion; an access window that is provided at the side wall portion of the platform unit an access window moving device that opens and closes the access window; a working device; and a control device that is provided at the outside of the reactor vessel and controls the access window moving device and the working device, wherein the control device drives the access window moving device to open the access window, drives the working device to perform work inside the nozzle stub, and then drives the access window moving device to close the access window after the performance of the work.Type: GrantFiled: May 26, 2010Date of Patent: December 20, 2016Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.Inventors: Atsushi Sugiura, Takumi Hori, Kenji Nishikawa, Ken Onishi, Noriaki Shimonabe, Satoshi Tsuzuki, Ikuo Wakamoto
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Publication number: 20160254831Abstract: An information processing device of the present disclosure includes a processor, a power source that supplies power, a proximity sensor that detects approach of an object, and an antenna that outputs an electromagnetic wave. The processor sets a maximum power of the electromagnetic wave from the antenna to a first value after the power source starts supplying the power, and then sets the maximum power of the electromagnetic wave from the antenna to a second value greater than the first value when the proximity sensor no longer detects approach of an object that has once been detected by the proximity sensor.Type: ApplicationFiled: July 1, 2014Publication date: September 1, 2016Inventor: Kenji NISHIKAWA
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Publication number: 20160133548Abstract: A semiconductor device, includes a die pad that has a first main surface and a second main surface located on the opposite side of the first main surface; a lead arranged next to the die pad; a semiconductor chip that has a surface, a first electrode and a second electrode formed on the surface, and a reverse side located on the opposite side of the surface, and is mounted on a chip mounting area of the first main of the die pad; a first wire that electrically couples the first electrode of the semiconductor chip and the lead; a second wire that electrically couples the second electrode of the semiconductor chip and the die pad; and a sealed body that seals the semiconductor chip, the first wire, and the second wire.Type: ApplicationFiled: January 16, 2016Publication date: May 12, 2016Inventors: Akito SHIMIZU, Kenji NISHIKAWA, Sadayuki MOROI, Tomoo lmura
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Publication number: 20160111357Abstract: A semiconductor device has a chip mounting part, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip is mounted over the chip mounting part in a direction in which its first principal plane faces the chip mounting part. A part of the second semiconductor chip is mounted over the chip mounting part in a direction in which its third principal plane faces the first semiconductor chip. The element mounting part has a notch part. A part of the second semiconductor chip overlaps the notch part. In a region of the third principal plane of the second semiconductor chip that overlaps the notch part, a second electrode pad is provided.Type: ApplicationFiled: December 29, 2015Publication date: April 21, 2016Applicant: Renesas Electronics CorporationInventors: Shinichi UCHIDA, Kenji NISHIKAWA, Masato KANNO, Mika YONEZAWA, Shunichi KAERIYAMA, Toshinori KIYOHARA
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Patent number: 9293396Abstract: A method for manufacturing a semiconductor device, includes: (a) preparing a lead frame that includes a die pad having a first plane and a second plane located on the opposite side of the first plane, and a plurality of leads arranged next to the die pad; (b) mounting a semiconductor chip having a surface, a plurality of electrodes formed over the surface, and a reverse side located on the opposite side of the surface over a chip mounting area of the first plane of the die pad; (c) electrically coupling parts of the electrodes of the semiconductor chip and the leads through a plurality of first wires and electrically coupling the other parts of the electrodes and the die pad through a second wire.Type: GrantFiled: March 16, 2015Date of Patent: March 22, 2016Assignee: Renesas Electronics CorporationInventors: Akito Shimizu, Kenji Nishikawa, Sadayuki Moroi, Tomoo Imura
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Patent number: 9257400Abstract: A semiconductor device has a chip mounting part, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip is mounted over the chip mounting part in a direction in which its first principal plane faces the chip mounting part. A part of the second semiconductor chip is mounted over the chip mounting part in a direction in which its third principal plane faces the first semiconductor chip. The element mounting part has a notch part. A part of the second semiconductor chip overlaps the notch part. In a region of the third principal plane of the second semiconductor chip that overlaps the notch part, a second electrode pad is provided.Type: GrantFiled: September 16, 2014Date of Patent: February 9, 2016Assignee: Renesas Electronics CorporationInventors: Shinichi Uchida, Kenji Nishikawa, Masato Kanno, Mika Yonezawa, Shunichi Kaeriyama, Toshinori Kiyohara
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Publication number: 20150376160Abstract: A novel ?-halogen-substituted thiophene compound or a pharmacologically acceptable salt thereof, which has a potent LPA receptor-antagonist activity and is useful as a medicament is provided. A compound represented by the general formula (I) wherein A represents, a phenyl ring, a thiophene ring, or an isothiazole ring; R1 is the same or different, and represents a halogen atom, or a C1-C3 alkyl group; R2 represents a hydrogen atom, or a C1-C6 alkyl group; p represents an integer of 0 to 5; V represents CR3 wherein R3 represents a hydrogen atom, an amino group, a nitro group, or a C1-C3 alkoxy group, or V represents a nitrogen atom; and X represents a halogen atom, or a salt thereof.Type: ApplicationFiled: June 26, 2015Publication date: December 31, 2015Applicant: UBE INDUSTRIES, LTD.Inventors: Noriaki IWASE, Hiroshi NISHIDA, Makoto OKUDO, Masaaki ITO, Shigeyuki KONO, Masaaki MATOYAMA, Shigeru USHIYAMA, Eiji OKANARI, Hirofumi MATSUNAGA, Kenji NISHIKAWA, Tomio KIMURA
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Publication number: 20150194368Abstract: A method for manufacturing a semiconductor device, includes: (a) preparing a lead frame that includes a die pad having a first plane and a second plane located on the opposite side of the first plane, and a plurality of leads arranged next to the die pad; (b) mounting a semiconductor chip having a surface, a plurality of electrodes formed over the surface, and a reverse side located on the opposite side of the surface over a chip mounting area of the first plane of the die pad; (c) electrically coupling parts of the electrodes of the semiconductor chip and the leads through a plurality of first wires and electrically coupling the other parts of the electrodes and the die pad through a second wire.Type: ApplicationFiled: March 16, 2015Publication date: July 9, 2015Inventors: Akito SHIMIZU, Kenji Nishikawa, Sadayuki Moroi, Tomoo Imura
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Publication number: 20150165531Abstract: A side milling cutter for slot cutting is provided whose vibration can be damped even in cases where a vibration mode of the cutter generates plural nodes in a cutting part. A side milling cutter for slot cutting of the present invention includes a disc-shaped cutter and a plurality of cartridges as cutting edges provided at a predefined interval in a circumferential direction along an outer circumference of the disc-shaped cutter. The disc-shaped cutter cuts a predefined slot on a workpiece using the cartridges by circumferentially rotating. The disc-shaped cutter internally includes a plurality of vibration damping structures in the circumferential direction on a disk surface of the disc-shaped cutter.Type: ApplicationFiled: December 18, 2014Publication date: June 18, 2015Inventors: Takayuki MIYAMOTO, Kenji NISHIKAWA, Ippei KONO, Junichi HIRAI, Masanori KAWAKAMI, Nobuhisa KANAMARU, Hitoshi TOHKAIRIN
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Patent number: 9029195Abstract: A method of manufacturing a semiconductor device includes mounting at least one of a first semiconductor chip and a second semiconductor chip over a die pad of a leadframe, and inspecting a mounting position of at least one of the first semiconductor chip and the second semiconductor chip, wherein the leadframe includes first mark formed to the die pad, for indicating a first mounting region for the first semiconductor chip, and second mark formed to the die pad, for indicating a second mounting region for the second semiconductor chip, the first mark is different from the second mark, in at least either one of size and geometry, wherein, in the inspecting a mounting position of at least one of the first semiconductor chip and the second semiconductor chip, a mounting position of the first semiconductor chip is inspected when the first semiconductor chip is mounted.Type: GrantFiled: May 2, 2014Date of Patent: May 12, 2015Assignee: Renesas Electronics CorporationInventor: Kenji Nishikawa
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Patent number: 9018745Abstract: A method according to the invention has a bonding process of mounting a semiconductor chip on an upper surface of a die pad that has the upper surface whose area is larger than a reverse side of the semiconductor chip. It also has a sealed body formation process of sealing the semiconductor chip so that an undersurface opposite to the upper surface of the die pad may be exposed after the bonding process. Here, the upper surface of the die pad is arranged around an area over which the semiconductor chip is mounted, and has a hollow part arrangement area in which a groove or multiple holes are formed. Moreover, surface roughness of the upper surface is made coarser than surface roughness of the undersurface.Type: GrantFiled: May 20, 2013Date of Patent: April 28, 2015Assignee: Renesas CorporationInventors: Akito Shimizu, Kenji Nishikawa, Sadayuki Moroi, Tomoo Imura
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Publication number: 20150084209Abstract: A semiconductor device has a chip mounting part, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip is mounted over the chip mounting part in a direction in which its first principal plane faces the chip mounting part. A part of the second semiconductor chip is mounted over the chip mounting part in a direction in which its third principal plane faces the first semiconductor chip. The element mounting part has a notch part. A part of the second semiconductor chip overlaps the notch part. In a region of the third principal plane of the second semiconductor chip that overlaps the notch part, a second electrode pad is provided.Type: ApplicationFiled: September 16, 2014Publication date: March 26, 2015Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Shinichi UCHIDA, Kenji NISHIKAWA, Masato KANNO, Mika YONEZAWA, Shunichi KAERIYAMA, Toshinori KIYOHARA
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Publication number: 20140242734Abstract: A method of manufacturing a semiconductor device includes mounting at least one of a first semiconductor chip and a second semiconductor chip over a die pad of a leadframe, and inspecting a mounting position of at least one of the first semiconductor chip and the second semiconductor chip, wherein the leadframe includes first mark formed to the die pad, for indicating a first mounting region for the first semiconductor chip, and second mark formed to the die pad, for indicating a second mounting region for the second semiconductor chip, the first mark is different from the second mark, in at least either one of size and geometry, wherein, in the inspecting a mounting position of at least one of the first semiconductor chip and the second semiconductor chip, a mounting position of the first semiconductor chip is inspected when the first semiconductor chip is mounted.Type: ApplicationFiled: May 2, 2014Publication date: August 28, 2014Applicant: Renesas Electronics CorporationInventor: Kenji Nishikawa
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Patent number: 8816927Abstract: A GPS antenna is provided with a reflective conductor portion. Thereby, an electromagnetic wave radiated from an antenna conductor portion in a predetermined direction can be grounded electrically, and thus radiation of the electromagnetic wave in a direction (arbitrary direction) opposite to the predetermined direction can be enhanced. As a result, the directivity of the electromagnetic wave in the arbitrary direction can be enhanced to improve the positioning accuracy.Type: GrantFiled: March 3, 2011Date of Patent: August 26, 2014Assignee: Panasonic CorporationInventors: Kazuya Nakano, Kenji Nishikawa, Kazuya Tani