Patents by Inventor Kenji Noda

Kenji Noda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090264611
    Abstract: Polybutylene terephthalate has an intrinsic viscosity of 0.7 to 1.0 dL/g and an end carboxyl group concentration of 0.1 to 18 ?eq/g, which is produced in a presence of a catalyst comprising a titanium compound and a metal compound containing a metal of Group 2A of the Periodic Table. In the preferable embodiment of the present invention, the polybutylene terephthalate has a crystallization temperature of 170 to 195° C. as measured at a temperature drop rate of 20° C./min using a differential scanning calorimeter, an end vinyl group concentration of not more than 10 ?eq/g, and not more than 10% of a solution haze of a solution prepared by dissolving 2.7 g of said polybutylene terephthalate in 20 mL of a mixed solvent containing phenol and tetrachloroethane at a weight ratio of 3:2.
    Type: Application
    Filed: March 29, 2005
    Publication date: October 22, 2009
    Inventors: Toshiyuki Hamano, Masanori Yamamoto, Shinichiro Matsuzono, Kenji Noda
  • Publication number: 20090259172
    Abstract: An over tube comprises an over tube body that has an inner diameter fitting over the outer diameter of an insertion part, and is flexible and expandable in the direction of the outer diameter, a gas supply port provided on the base end side of the over tube body, an expansion/contraction part that is formed integrally with the gas supply port, provided to communicate from the base end side to a predetermined position on a distal end side, and can expand in the direction of the outer diameter by injecting a gas from the gas supply port, and at least one channel that is provided between the inner and the outer diameters of the over tube body, and penetrates from the distal end of the over tube through the base end side.
    Type: Application
    Filed: April 9, 2008
    Publication date: October 15, 2009
    Inventors: Koji YAMAOKA, Kenji NODA, Masatsugu OYAMA, Kunitoshi HIRAGA
  • Patent number: 7582394
    Abstract: A photomask includes, on a translucent substrate, three or more first light-shielding portions each in insular shape having a property of shielding exposure light and spaced equidistantly, a second light-shielding portion having a property of shielding the exposure light and formed to connect the adjacent first light-shielding portions, and first light-transmitting portions each in slit shape having a property of transmitting the exposure light and formed to be surrounded with the first and second light-shielding portions. The second light-shielding portion is formed to contain a point located equidistantly from the three or more first light-shielding portions.
    Type: Grant
    Filed: October 5, 2004
    Date of Patent: September 1, 2009
    Assignee: Panasonic Corporation
    Inventors: Kenji Noda, Shin Hashimoto
  • Publication number: 20090213650
    Abstract: A nonvolatile semiconductor memory device includes a latch circuit including a first inverter and a second inverter cross-coupled to each other, a source node of a MIS transistor of the first inverter and a source node of a MIS transistor of the second inverter being both coupled to a plate line, and a control circuit configured to apply a first potential to the plate line in a store mode to cause a change in threshold voltage to one of the MIS transistors, and configured to apply a second potential to the plate line in a power-on mode to cause the latch circuit to latch data responsive to the change in threshold voltage generated in the store mode, such that the data latched by the latch circuit in the power-on mode is automatically output to outside the nonvolatile semiconductor memory device upon power-on thereof.
    Type: Application
    Filed: February 25, 2008
    Publication date: August 27, 2009
    Applicant: NSCore Inc.
    Inventor: Kenji NODA
  • Publication number: 20090213664
    Abstract: A nonvolatile semiconductor memory device includes a latch circuit having two nodes, a nonvolatile memory cell including two MIS transistors, a bit swapping unit configured to provide straight connections between the two nodes and the two MIS transistors during a first operation mode and to provide cross connections between the two nodes and the two MIS transistors during a second operation mode, and a control circuit configured to cause, in one of the first and second operation modes, the nonvolatile memory cell to store the data latched in the latch circuit as an irreversible change of transistor characteristics occurring in a selected one of the two MIS transistors, and further configured to cause, in another one of the first and second operation modes, the latch circuit to detect the data stored in the nonvolatile memory cell.
    Type: Application
    Filed: February 26, 2008
    Publication date: August 27, 2009
    Inventors: Takashi KIKUCHI, Kenji NODA
  • Publication number: 20090197189
    Abstract: In a focus measurement method and a method of manufacturing a semiconductor device relating to the present invention, a focus value is obtained by using a fluctuation where shrinkage of a resist pattern by an electron beam irradiation depends upon the focus value. In the case of obtaining the focus value, the shrinkage of the resist pattern for a focus measurement formed by exposure to be subject for a focus value measurement is measured. The focus value corresponding to the shrinkage is obtained from the pre-obtained focal dependency of the shrinkage. A focal shift length can be defined from a difference between the focus value and a predetermined best focus value.
    Type: Application
    Filed: January 23, 2009
    Publication date: August 6, 2009
    Inventors: Rimiko IDE, Kenji NODA, Hirofumi FUKUMOTO, Kenichi ASAHI, Naohiko UJIMARU
  • Patent number: 7569027
    Abstract: A gas supply apparatus is provided and has first and second fittings and first and second tubes. The first fitting is provided to discharge a gas of a first pressure therethrough, while the second fitting is provided to discharge a gas of a second pressure therethrough. The first tube has one end to which a first connector connectable to the first fitting is attached and supplies the first-pressure gas to a first body cavity of a subject. The second tube has one end to which a second connector connectable to the second fitting is attached and supplies the second-pressure gas to a second body cavity of the subject. The apparatus may comprise an erroneous-connection preventing device preventing an erroneous connection including at least one of a connection of the first connector to the second fitting and a further connection of the second connector to the first fitting.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: August 4, 2009
    Assignee: Olympus Corporation
    Inventors: Takefumi Uesugi, Daisuke Sano, Atsuhiko Kasahi, Kenji Noda
  • Patent number: 7558997
    Abstract: To provide wiring structure and method capable of supplying a scan clock signal for each clock domain without requesting a user to add a test circuit. The wiring structure of a semiconductor integrated circuit according to an embodiment of the present invention includes: a fixed layer where a common line independent of a user circuit is formed; and a customized layer which is formed on the fixed layer and in which a line dependent on the user circuit is formed. The fixed layer is provided with a scan clock line supplying a scan clock signal for scan test to the selecting circuit, and a clock line supplying an output signal of the selecting circuit to a flip-flop of a scan path, and the customized layer is provided with a user clock line supplying a user clock signal to the selecting circuit.
    Type: Grant
    Filed: October 10, 2006
    Date of Patent: July 7, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Kenji Noda
  • Publication number: 20090154248
    Abstract: A nonvolatile memory device includes a pair of PMOS transistors, and a control circuit configured to operate in a store mode to apply to a first one of the PMOS transistors potentials that cause an NBTI degradation purposefully and to apply to a second one of the PMOS transistors potentials that cause no NBTI degradation while causing no current to flow between a source node and a drain node of the first one of the PMOS transistors, and to operate in a recall mode to set gate nodes of the PMOS transistors to a common potential to detect a difference in the NBTI degradation between said PMOS transistors.
    Type: Application
    Filed: October 3, 2005
    Publication date: June 18, 2009
    Inventor: Kenji Noda
  • Publication number: 20090130434
    Abstract: A surface coated tool including a substrate, and stacked layers composed of two coating layers represented by the following general formula (1) on the substrate is provided. A first coating layer to be coated on the surface of the substrate, which has a thickness of 0.1 to 1 ?m, is composed of a granular crystal having a mean crystal diameter of 0.01 to 0.1 ?m. A second coating layer to be coated on the surface of the first coating layer, which has a thickness of 0.5 to 5 ?m, is composed of columnar crystal grown in a direction perpendicular to the substrate, and the columnar crystal has a mean crystal width of 0.05 to 0.3 ?m in a direction parallel to the substrate while a mean crystal width thereof is larger than the mean crystal diameter of the first coating layer.
    Type: Application
    Filed: March 26, 2007
    Publication date: May 21, 2009
    Applicant: KYOCERA CORPORATION
    Inventors: Yaocan Zhu, Kenji Noda, Masahito Matsuzawa
  • Patent number: 7518917
    Abstract: A nonvolatile semiconductor memory device includes a latch configured to store data, a plurality of word lines, a driver configured to activate one of the plurality of word lines, and a plurality of nonvolatile memory cells coupled to the respective word lines, each of the nonvolatile memory cells coupled to the latch so as to exchange stored data with the latch upon activation of a corresponding one of the word lines, each of the nonvolatile memory cells including two MIS transistors and configured to store data as an irreversible change of transistor characteristics occurring in one of the two MIS transistors, wherein the driver includes at least one nonvolatile memory cell storing count data responsive to a number of times storing of data has been performed with respect to the plurality of nonvolatile memory cells, and is configured to activate one of the word lines indicated by the count data.
    Type: Grant
    Filed: July 11, 2007
    Date of Patent: April 14, 2009
    Assignee: NScore Inc.
    Inventors: Kenji Noda, Takashi Kikuchi
  • Publication number: 20090087607
    Abstract: The present invention has its object to provide a resin composition for tubes excellent in balance among wear resistance, flexibility, gas permeation resistance and low resilience (pliability). The object is accomplished by a resin composition for tubes which comprises an isobutylene block copolymer (A) constituted of a polymer block (a) derived from isobutylene as the constituent and a polymer block (b) derived from a monomer component other than isobutylene, and a thermoplastic polyurethane resin (B).
    Type: Application
    Filed: December 1, 2005
    Publication date: April 2, 2009
    Applicant: KANEKA CORPORATION
    Inventors: Kenji Noda, Tsuyoshi Mihayashi, Kazumasa Ohara
  • Publication number: 20090054618
    Abstract: An object of the present invention is to provide polybutylene terephthalate which has excellent color tone, hydrolysis resistance, heat stability, transparency and moldability as well as a less content of impurities, can be produced with maintaining its productivity while preventing from generation of tetrahydrofuran as a by-product, and can be suitably applied to films, monofilaments, fibers, electric and electronic parts, automobile parts, etc.
    Type: Application
    Filed: August 28, 2006
    Publication date: February 26, 2009
    Inventors: Kenji Noda, Masanori Yamamoto, Shinichiro Matsuzono, Toshiyuki Hamano, Yoshio Akahane, Hidekazu Shouji
  • Patent number: 7483290
    Abstract: A nonvolatile semiconductor memory device includes a control circuit, an inverting circuit, and memory units, each of the memory units including a latch having a first node and a second node, a plate line, a first MIS transistor having one of source/drain nodes coupled to the first node of the latch, another one of the source/drain nodes coupled to the plate line, and a gate node coupled to a word line, and a second MIS transistor having one of source/drain nodes coupled to the second node of the latch, another one of the source/drain nodes coupled to the plate line, and a gate node coupled to the word line, wherein the control circuit is configured to invert the data latched in the latch by reading the data from the latch, causing the inverting circuit to invert the read data, and writing the inverted data to the latch.
    Type: Grant
    Filed: February 2, 2007
    Date of Patent: January 27, 2009
    Assignee: NSCORE Inc.
    Inventors: Takashi Kikuchi, Kenji Noda
  • Publication number: 20090016105
    Abstract: A nonvolatile semiconductor memory device includes a latch configured to store data, a plurality of word lines, a driver configured to activate one of the plurality of word lines, and a plurality of nonvolatile memory cells coupled to the respective word lines, each of the nonvolatile memory cells coupled to the latch so as to exchange stored data with the latch upon activation of a corresponding one of the word lines, each of the nonvolatile memory cells including two MIS transistors and configured to store data as an irreversible change of transistor characteristics occurring in one of the two MIS transistors, wherein the driver includes at least one nonvolatile memory cell storing count data responsive to a number of times storing of data has been performed with respect to the plurality of nonvolatile memory cells, and is configured to activate one of the word lines indicated by the count data.
    Type: Application
    Filed: July 11, 2007
    Publication date: January 15, 2009
    Inventors: Kenji NODA, Takashi KIKUCHI
  • Patent number: 7476213
    Abstract: In a gas supply system, a selection unit is configured to send an instruction to select any one of first gas and second gas. In the gas supply system, a controller is operative to control at least one of a first gas supply unit for supplying the first gas and a second gas supply unit for supplying the second gas to selectively insufflate any one of the first gas and second gas into a body based on the instruction sent from the selection unit.
    Type: Grant
    Filed: July 1, 2005
    Date of Patent: January 13, 2009
    Assignee: Olympus Corporation
    Inventors: Takefumi Uesugi, Daisuke Sano, Yoshimine Kobayashi, Mutsumi Ohshima, Takehiro Nishiie, Atsuhiko Kasahi, Kenji Noda
  • Patent number: 7426016
    Abstract: According to an exposure apparatus and an exposure method in the present invention, based on a focus value and a leveling value in each exposure shot calculated based on measurements by a focus sensor, differential absolute value for respective value are calculated. The differential absolute values for the focus values and leveling vaule are compared with predetermined threshold vaule for the respective differential absolute values. When the differential absolute values exceed the threshold value, it is determined that an exposure abnormality exists. In such case, based at least the number of exposure area where the exposure abnormality is occurred and distribution of the exposure area where the exposure abnormality is occurred on the object to be exposed, a kind of the exposure abnormality is identifed. The detection of the exposure abnormality is assured, and a cause of the abnormality is determined without lowering manufacturing capabilities and increasing in cost.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: September 16, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Noritoshi Takada, Seiji Tanaka, Kenji Noda, Hidekazu Kitahara
  • Patent number: 7414903
    Abstract: A nonvolatile semiconductor memory device includes a memory cell having a MIS transistor configured to experience an irreversible change in transistor characteristics thereof to store data as the irreversible change, the MIS transistor having a gate node coupled to a word selecting line and a source/drain node coupled to a bit line, and the MIS transistor becoming conductive in response to a first state of the word selecting line and becoming nonconductive in response to a second state of the word selecting line, and a test circuit coupled to the bit line to sense a current running through the MIS transistor, the test circuit configured to indicate error in response to either a detection of presence of the current when the word selecting line is in the second state or a detection of absence of the current when the word selecting line is in the first state.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: August 19, 2008
    Assignee: Nscore Inc.
    Inventor: Kenji Noda
  • Patent number: 7413499
    Abstract: A process of grinding a surface of a workpiece, by a grinding tool rotated about its axis. The process includes a grinding step of grinding the workpiece surface, by pressing at least one of the grinding tool and the workpiece against the other of the grinding tool and the workpiece, such that a constant force is exerted on the other of the grinding tool and the workpiece by the at least one of the grinding tool and the workpiece. Also disclosed is a grinding apparatus including: a moving device operable to move at least one of the grinding tool and the workpiece relative to the other of the grinding tool and the workpiece, at least in an infeed direction that increases a depth of cut of the grinding tool into the workpiece; and a controller which controls the moving device, such that the at least one of the grinding tool and the workpiece is pressed against the other of the grinding tool and the workpiece, with a constant force.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: August 19, 2008
    Assignee: Noritake Co., Limited
    Inventor: Kenji Noda
  • Publication number: 20080186767
    Abstract: A nonvolatile semiconductor memory device includes a control circuit, an inverting circuit, and memory units, each of the memory units including a latch having a first node and a second node, a plate line, a first MIS transistor having one of source/drain nodes coupled to the first node of the latch, another one of the source/drain nodes coupled to the plate line, and a gate node coupled to a word line, and a second MIS transistor having one of source/drain nodes coupled to the second node of the latch, another one of the source/drain nodes coupled to the plate line, and a gate node coupled to the word line, wherein the control circuit is configured to invert the data latched in the latch by reading the data from the latch, causing the inverting circuit to invert the read data, and writing the inverted data to the latch.
    Type: Application
    Filed: February 2, 2007
    Publication date: August 7, 2008
    Inventors: Takashi Kikuchi, Kenji Noda