Patents by Inventor Kenji Sakaue

Kenji Sakaue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9443602
    Abstract: According to one embodiment, a storage device includes a storage medium, a DLL circuit, a latch circuit, and a delay amount adjustment circuit. The DLL circuit gives a predetermined amount of delay to an inputted clock signal, the latch circuit latches data outputted from the storage medium in accordance with the clock signal delayed in the DLL circuit, the delay amount adjustment circuit adjusts the delay amount that the DLL circuit is to give to the clock signal based on a latch result by the latch circuit.
    Type: Grant
    Filed: November 29, 2013
    Date of Patent: September 13, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Sakaue, Edward Bandy Samigat, Atsushi Takayama, Yutaka Tango
  • Patent number: 9312885
    Abstract: According to one embodiment, a memory system includes a memory cell array, first error correction part, second error correction part, and third error correction part. The memory cell array includes a first storage area in which 1-bit data is stored in one memory cell, and second storage area in which data of a plurality of bits is stored in one memory cell. When data is written to the first storage area, the first error correction part generates first parity data in the row direction on the basis of the data described above. The second error correction part corrects an error of the data described above on the basis of the first parity data read from the memory cell array. The third error correction part generates second parity data in the column direction on the basis of data of a plurality of pages.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: April 12, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenji Sakaue, Yoshihisa Kondo, Tarou Iwashiro
  • Publication number: 20160020787
    Abstract: According to one embodiment, a parallel processor performs the row processes in parallel in a LDPC decode while performing the column processes in parallel in the LDPC decode, and a control circuit alternately repeats the parallel processes of the row process and the parallel processes of the column process as many times as the number of rows and columns in a check matrix and divides the parallel rows for the row process when the LDPC decode is started.
    Type: Application
    Filed: November 3, 2014
    Publication date: January 21, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuyuki ISHIKAWA, Kazuhiro ICHIKAWA, Toshihiko KITAZUME, Kenji SAKAUE, Kouji SAITOU
  • Patent number: 9195536
    Abstract: According to one embodiment, an error correction decoder includes a storage unit and parity check circuit. The storage unit stores first reliability information corresponding to a hard decision result of each of a plurality of bits which form an ECC (Error Correction Code) frame defined by a parity check matrix, and second reliability information corresponding to a soft decision result of each of the plurality of bits. The storage unit includes a register configured to allow the parity check circuit to steadily read out at least the first reliability information. The parity check circuit executes parity checking of a temporary estimated word based on the first reliability information using the parity check matrix. The parity check circuit executes parity checking once or more before completion of row processing and column processing of the entire parity check matrix by a calculation circuit for each trial of iterative decoding.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: November 24, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kenji Sakaue
  • Patent number: 9189322
    Abstract: According to one embodiment, a memory module which includes a plurality of nonvolatile memory cells with a plurality of pages and line-and-space word lines to which more than one of the memory cells are connected, and a controller which receives write data from a host device.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 17, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kenji Sakaue
  • Publication number: 20150254130
    Abstract: According to an embodiment, an error correction decoder includes a first calculation circuit and a second calculation circuit. The first calculation circuit and the second calculation circuit perform the column processing based on the second reliability information corresponding to variable nodes belonging to each of one or more valid blocks arranged in a first row group and the row processing based on the first reliability information corresponding to variable nodes belonging to one or more valid blocks arranged in a second row group whose processing order is later than that of the first row group in parallel.
    Type: Application
    Filed: March 7, 2014
    Publication date: September 10, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kenji SAKAUE, Kouji Saitou, Tatsuyuki Ishikawa, Kazuhiro Ichikawa, Naoaki Kokubun, Hironori Uchikawa
  • Publication number: 20150227419
    Abstract: According to one embodiment, an error correction decoder includes a selecting section, calculating section, check section, and updating section. The selecting section selects data used for matrix processing applied to a process target row from LLR data stored in the first memory section based on a check matrix, and stores the data in a second memory section. The calculating section executes the matrix processing based on the data stored in the second memory section, and writes updated data back to the second memory section. The check section checks a parity based on a calculating result of the calculating section. The updating section updates the LLR data of the first memory section based on the updated data of the second memory section.
    Type: Application
    Filed: June 19, 2014
    Publication date: August 13, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kenji Sakaue, Kouji Saitou, Tatsuyuki Ishikawa, Kazuhiro Ichikawa, Naoaki Kokubun, Hironori Uchikawa
  • Patent number: 9015548
    Abstract: In an error detection correction method of an embodiment, in decoding processing using a sum-product algorithm, which repeats processing of propagating reliability ? from a check node set to correspond to a Tanner graph of a check matrix of a low density parity check code to a plurality of bit nodes connected to the check node, and processing of propagating reliability ? from a bit node to a plurality of check nodes connected to the bit node, the check node includes a parity of two bits or more.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: April 21, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kenji Sakaue
  • Publication number: 20150058705
    Abstract: According to one embodiment, a storage device includes a storage medium, a DLL circuit, a latch circuit, and a delay amount adjustment circuit. The DLL circuit gives a predetermined amount of delay to an inputted clock signal, the latch circuit latches data outputted from the storage medium in accordance with the clock signal delayed in the DLL circuit, the delay amount adjustment circuit adjusts the delay amount that the DLL circuit is to give to the clock signal based on a latch result by the latch circuit.
    Type: Application
    Filed: November 29, 2013
    Publication date: February 26, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kenji SAKAUE, Edward Bandy SAMIGAT, Atsushi TAKAYAMA, Yutaka TANGO
  • Publication number: 20150012795
    Abstract: According to one embodiment, an error correction decoder includes a storage unit and parity check circuit. The storage unit stores first reliability information corresponding to a hard decision result of each of a plurality of bits which form an ECC (Error Correction Code) frame defined by a parity check matrix, and second reliability information corresponding to a soft decision result of each of the plurality of bits. The storage unit includes a register configured to allow the parity check circuit to steadily read out at least the first reliability information. The parity check circuit executes parity checking of a temporary estimated word based on the first reliability information using the parity check matrix. The parity check circuit executes parity checking once or more before completion of row processing and column processing of the entire parity check matrix by a calculation circuit for each trial of iterative decoding.
    Type: Application
    Filed: November 22, 2013
    Publication date: January 8, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Kenji Sakaue
  • Patent number: 8856613
    Abstract: According to one embodiment, a semiconductor storage device includes a semiconductor memory which includes two or more cell peripheral circuits and two or more storage cells at least one of reading and writing of which is controlled by the cell peripheral circuits in each of the cell peripheral circuits. Further, the semiconductor storage device includes a memory control unit configured to instruct to form 1 symbol as a unit for creating an error correction code by the data held by the storage cells controlled by the same cell peripheral circuit and creating an error correction code to the symbol created base of the instruction.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: October 7, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Sakaue, Yoshio Mochizuki
  • Publication number: 20140298142
    Abstract: A memory controller including a buffer configured to perform decoding frame-unit data decoded by an LDPC decoder through partial parallel processing based on a check matrix made up of a block of a unit matrix and a plurality of blocks in which each row of the unit matrix is sequentially shifted and store threshold decision information of the data read from a memory section, an LLR conversion section configured to convert the threshold decision information to an LLR, an LMEM configured to store probability information ? calculated during iteration processing that repeatedly performs column processing and row processing based on the LLR in an iteration unit equal to or smaller than a size of the block, and a CPU core configured to transfer the probability information ? stored in the LMEM to the buffer every time the iteration processing in the iteration unit is completed.
    Type: Application
    Filed: June 12, 2014
    Publication date: October 2, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenji SAKAUE, Atsushi TAKAYAMA, Yoshihisa KONDO, Tatsuyuki ISHIKAWA
  • Publication number: 20140281794
    Abstract: According to one embodiment, an error correction circuit includes a first memory module, a read-out module, a first arithmetic module, a detector, a second arithmetic module, and a transfer module. The first memory module stores logarithmic likelihood ratio (LLR) data to which low density parity check codes (LDPC) data has been converted. The read-out module reads out, from the first memory module, the LLR data of a plurality of variable nodes which are connected to a selected check node, based on a check matrix. The first and second arithmetic modules update the LLR data, based on the read-out LLR data and first and second reliability data. The transfer module transfers the updated LLR data to the first memory module.
    Type: Application
    Filed: August 9, 2013
    Publication date: September 18, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kenji SAKAUE
  • Patent number: 8782496
    Abstract: A memory controller including a buffer configured to perform decoding frame-unit data decoded by an LDPC decoder through partial parallel processing based on a check matrix made up of a block of a unit matrix and a plurality of blocks in which each row of the unit matrix is sequentially shifted and store threshold decision information of the data read from a memory section, an LLR conversion section configured to convert the threshold decision information to an LLR, an LMEM configured to store probability information ? calculated during iteration processing that repeatedly performs column processing and row processing based on the LLR in an iteration unit equal to or smaller than a size of the block, and a CPU core configured to transfer the probability information ? stored in the LMEM to the buffer every time the iteration processing in the iteration unit is completed.
    Type: Grant
    Filed: September 18, 2011
    Date of Patent: July 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Sakaue, Atsushi Takayama, Yoshihisa Kondo, Tatsuyuki Ishikawa
  • Publication number: 20140068379
    Abstract: According to one embodiment, a memory module which includes a plurality of nonvolatile memory cells with a plurality of pages and line-and-space word lines to which more than one of the memory cells are connected, and a controller which receives write data from a host device.
    Type: Application
    Filed: March 14, 2013
    Publication date: March 6, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Kenji SAKAUE
  • Publication number: 20140053041
    Abstract: According to one embodiment, a memory system includes a memory cell array, first error correction part, second error correction part, and third error correction part. The memory cell array includes a first storage area in which 1-bit data is stored in one memory cell, and second storage area in which data of a plurality of bits is stored in one memory cell. When data is written to the first storage area, the first error correction part generates first parity data in the row direction on the basis of the data described above. The second error correction part corrects an error of the data described above on the basis of the first parity data read from the memory cell array. The third error correction part generates second parity data in the column direction on the basis of data of a plurality of pages.
    Type: Application
    Filed: November 8, 2012
    Publication date: February 20, 2014
    Inventors: Kenji SAKAUE, Yoshihisa Kondo, Tarou Iwashiro
  • Patent number: 8589756
    Abstract: A memory card according to an embodiment includes: a memory section having a binary storage area (SLC area) and a multi-value storage area (MLC area); an error correction section configured to correct an error of data stored in the MLC area; and an erasure correction section configured to store, in the SLC area, the position information on the multi-value memory cell storing the data having the error detected by the error correction section and configured to perform erasure correction on the basis of the position information.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: November 19, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukio Ishikawa, Kenji Sakaue
  • Publication number: 20130242656
    Abstract: A memory controller includes a processor that includes a monitoring module, a control module, and a parity generating module. The monitoring module receives a data sequence and checks the data sequence for a designated pattern. The control module determines page size of data sequences that include the designated pattern and arranges an idle area for each page based on the total data quantity and the size of the data sequence, where the data quantity of the data stored in each page is uniform. The parity generating module generates the extended parity in the idle area based on a portion of the data stored in each page and the management information of the page. In each page, the control module stores a portion of the data and the extended parity in the idle area.
    Type: Application
    Filed: August 31, 2012
    Publication date: September 19, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenji SAKAUE, Taro IWASHIRO
  • Patent number: 8453034
    Abstract: An LDPC error detection/correction circuit according to an embodiment includes a selector that divides data into p groups based on a check matrix H including blocks made up of unit matrixes having a size p and shift blocks, a selector that divides a group into Y subgroups, a bit node storage section that stores LMEM variables to calculate a probability ? in association with each first address, a check node storage section that stores TMEM variables to calculate an external value ? in association with each second address, a rotator that performs rotation processing on the TMEM with a rotation value based on a shift value, and an operation circuit made up of (p/Y) operation units that perform parallel processing in subgroup units.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: May 28, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Sakaue, Tatsuyuki Ishikawa, Yukio Ishikawa, Kazuhiro Ichikawa, Hironori Uchikawa
  • Patent number: 8448050
    Abstract: A memory system having a memory card configured to store frame data composed of a plurality of pieces of sector data and a host configured to send and receive the frame data to and from the memory card, the memory card includes: an ECC1 decoder configured to perform BCH decoding processing with a hard decision code on a sector data basis; an ECC2 decoder configured to perform LDPC decoding processing with an LDPC code on a frame data basis; a sector error flag section configured to store information about presence or absence of error data in the BCH decoding processing; and an ECC control section configured to perform, in the LDPC decoding processing, control of increasing a reliability of sector data containing no error data based on the information in the sector error flag section.
    Type: Grant
    Filed: June 1, 2010
    Date of Patent: May 21, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Sakaue, Tatsuyuki Ishikawa, Kazuhiro Ichikawa