Abstract: A memory card according to an embodiment includes: a memory section having a binary storage area (SLC area) and a multi-value storage area (MLC area); an error correction section configured to correct an error of data stored in the MLC area; and an erasure correction section configured to store, in the SLC area, the position information on the multi-value memory cell storing the data having the error detected by the error correction section and configured to perform erasure correction on the basis of the position information.

Abstract: According to one embodiment, a semiconductor storage device includes a semiconductor memory which includes two or more cell peripheral circuits and two or more storage cells at least one of reading and writing of which is controlled by the cell peripheral circuits in each of the cell peripheral circuits. Further, the semiconductor storage device includes a memory control unit configured to instruct to form 1 symbol as a unit for creating an error correction code by the data held by the storage cells controlled by the same cell peripheral circuit and creating an error correction code to the symbol created base of the instruction.

Abstract: In an error detection correction method of an embodiment, in decoding processing using a sum-product algorithm, which repeats processing of propagating reliability ? from a check node set to correspond to a Tanner graph of a check matrix of a low density parity check code to a plurality of bit nodes connected to the check node, and processing of propagating reliability ? from a bit node to a plurality of check nodes connected to the bit node, the check node includes a parity of two bits or more.

Abstract: A computer-implemented system for trading a viatical and life settlement insurance policy receives a seller's selling price for the policy; divides the policy into a plurality of units; determines a price of one unit based on the number of units; receives a purchase price of the policy from at least one potential purchaser; makes an initial determination of the number of units bought by the potential purchaser in order to be allocated depending on the purchase price; compares the total number of units allocated to the potential purchaser with the total number of units into which the policy was divided; adjusts the price of one unit based on this comparison; and redetermines the number of units allocated to the potential purchaser, depending on the adjusted purchase price. The system repeats making the comparison, the price adjustment, and the redetermination for a given amount of time.

Abstract: An LDPC error detection/correction circuit according to an embodiment includes a selector that divides data into p groups based on a check matrix H including blocks made up of unit matrixes having a size p and shift blocks, a selector that divides a group into Y subgroups, a bit node storage section that stores LMEM variables to calculate a probability ? in association with each first address, a check node storage section that stores TMEM variables to calculate an external value ? in association with each second address, a rotator that performs rotation processing on the TMEM with a rotation value based on a shift value, and an operation circuit made up of (p/Y) operation units that perform parallel processing in subgroup units.

Abstract: A memory system having a memory card configured to store frame data composed of a plurality of pieces of sector data and a host configured to send and receive the frame data to and from the memory card, the memory card includes: an ECC1 decoder configured to perform BCH decoding processing with a hard decision code on a sector data basis; an ECC2 decoder configured to perform LDPC decoding processing with an LDPC code on a frame data basis; a sector error flag section configured to store information about presence or absence of error data in the BCH decoding processing; and an ECC control section configured to perform, in the LDPC decoding processing, control of increasing a reliability of sector data containing no error data based on the information in the sector error flag section.

Abstract: A memory controller that has an error correction number correspondence table that stores an error threshold level in correspondence with an error correction number; an error threshold level storage section that stores an error threshold level for each block; an uncorrected number measurement section that measures an uncorrected number of an error correction for each block; an error threshold level modification section that, each time an uncorrected number of a certain block exceeds a predetermined number, modifies the error threshold level of the block; an encoder that performs encoding processing of data stored in memory cells belonging to each block with an error correction number that is based on an error threshold level and the error correction number correspondence table; and a decoder that performs decoding processing of data.

Abstract: An error detector/corrector includes an ECC cache unit configured to store an error bit address which represents an error location by associating the error bit address with an error page address and a coefficient ? of an error location polynomial; a comparison unit configured to check for a match by comparing new values with stored values, where the new values are an error page address detected by a syndrome calculation unit and a coefficient ? of the error location polynomial calculated by a polynomial calculation unit while the stored values are an error page address and a coefficient ? of the error location polynomial stored in the ECC cache unit; and a first error localization unit configured to identify a location of the error bit address stored in the ECC cache unit as the error location when the comparison unit determines that the compared values match.

Abstract: An information processing apparatus has a multi-valued NAND nonvolatile memory including a plurality of word lines and a plurality of memory cells connected to the respective word lines. Each memory cell has a plurality of threshold voltages, and is divided into a first and a second storage area. A program code is stored in the first storage area, and user data is stored in the second storage area. The apparatus also includes a volatile memory to which the program code is transferred from the multi-valued NAND nonvolatile memory. The apparatus further includes a CPU connected to the volatile memory and configured to operate based on the program code transferred to the volatile memory.

Abstract: To provide a medical cost adjusting method for suppressing a medical cost to a reasonable price so that a person who suffers from a disease can receive an appropriate medical service even if the person is not insured. A medical institution presents a predicted medical cost to be demanded therefrom for a medical service given to a patient as a desired demanding amount and, on the other hand, the patient, who desires to receive the medical service, presents a payable medical cost as a desired medical treatment amount, thus, matching of the desired demanding amount to the desired medical treatment amount is carried out. Accordingly, it is possible of integrating a reverse auction and a regular auction making it possible of efficiently collect members concerned in the auction trade. In the reverse auction, a medical cost is used as an article of trade between a medical institution and a patient.

Abstract: An information processing apparatus has a multi-valued NAND nonvolatile memory including a plurality of word lines and a plurality of memory cells connected to the respective word lines. Each memory cell has a plurality of threshold voltages, and is divided into a first and a second storage area. A program code is stored in the first storage area, and user data is stored in the second storage area. The apparatus also includes a volatile memory to which the program code is transferred from the multi-valued NAND nonvolatile memory. The apparatus further includes a CPU connected to the volatile memory and configured to operate based on the program code transferred to the volatile memory.

Abstract: A memory system including a nonvolatile semiconductor memory device and a controller. The memory device includes a plurality of word lines; and a plurality of memory cells each connected to a corresponding one of the word lines and each having N threshold voltages for storing multi-valued level, where N is a natural number of 4 or greater; wherein stored data in each of the plurality of memory cells constitutes a plurality of pages, at least only a part of multi-value level is used for storing data, a data “1” is always written to a lower page, a “0” or “1” binary data is written to an upper page, the same data is written in each of the pages when writing in the nonvolatile memory device, and only part of the pages to which the same data is written is accessed when reading out the nonvolatile memory device.

Abstract: An auction system between a seller and a bidder via a communication network, for calculating a proper price of a viatical and life settlement policy based on the amount of insurance carried by an insured, the estimated remaining life of the insured, an insurance premium due to be paid by the insured, a commission fee of an investment trust institution and the annual interest of the policy, for preventing the policy from being set at an illegally low price and allowing the insured to sell the policy at an optimized market price while maintaining a fair trade. Whether or not already-distributed key information is used for login, charges can be withdrawn from a trade account available for online settlement, and it is possible to confirm whether a seller or bidder has carried out an illegal action, so that troubles such as unpaid fees can be greatly reduced.

Abstract: An ECC control apparatus is to be connected between a host and a memory. The apparatus comprises a first input/output circuit, a detecting circuit, a code-generating circuit, a code-inserting circuit, a second input/output circuit. The first input/output circuit inputs and outputs data to and from the host. The detecting circuit detects a protected-data region and a redundant region of write data input to the first input/output circuit and having a predetermined data length. The code-generating circuit generates an error-correction code for correcting errors in data stored in the protected-data region. The code-inserting circuit inserts the error-correction code in the redundant region. The second input/output circuit inputs and outputs data to and from the memory.

Abstract: A processor boot-up controller includes: a volatile memory connected to a nonvolatile memory; a selector, which transfers boot-up codes to the volatile memory from the nonvolatile memory; a controller for the nonvolatile memory configured from a boot-up control sequencer, which transmits CPU read-in data to the CPU and brings the CPU into a wait state until boot-up code transfer completes; and an error detection and correction unit connected to the external CPU and the nonvolatile memory. The processor boot-up controls the CPU by reading data from the nonvolatile memory. The processor enables the CPU to access a SRAM in the shortest time in sync with the SRAM's ready timing, resulting in a reduction of average system boot-up time. An information processing system can use the controller for example for a nonvolatile memory, a microprocessor boot-up controller, and multi-valued nonvolatile memory.

Abstract: An information processing apparatus has a multi-valued NAND nonvolatile memory including a plurality of word lines and a plurality of memory cells connected to the respective word lines. Each memory cell has a plurality of threshold voltages, and is divided into a first and a second storage area. A program code is stored in the first storage area, and user data is stored in the second storage area. The apparatus also includes a volatile memory to which the program code is transferred from the multi-valued NAND nonvolatile memory. The apparatus further includes a CPU connected to the volatile memory and configured to operate based on the program code transferred to the volatile memory.

Abstract: A nonvolatile semiconductor memory controller has a plurality of word lines and a plurality of memory cells. Each memory cell is connected to a corresponding one of the word lines, and each memory cell has N threshold voltages, where N is a natural number of 4 or greater. The plurality of memory cells constitutes a plurality of pages, the same data is written in each of the pages when writing in the nonvolatile memory, and only part of the pages to which the same data is written is accessed when reading out the nonvolatile memory.

Abstract: To provide a medical cost adjusting method for suppressing a medical cost to a reasonable price so that a person who suffers from a disease can receive an appropriate medical service even if the person is not insured. A medical institution presents a predicted medical cost to be demanded therefrom for a medical service given to a patient as a desired demanding amount and, on the other hand, the patient, who desires to receive the medical service, presents a payable medical cost as a desired medical treatment amount, thus, matching of the desired demanding amount to the desired medical treatment amount is carried out. Accordingly, it is possible of integrating a reverse auction and a regular auction making it possible of efficiently collect members concerned in the auction trade. In the reverse auction, a medical cost is used as an article of trade between a medical institution and a patient.

Abstract: To enable a commercial trade wherein information about dealing an optional life settlement policy is disclosed transparently and fairly, and deal the life settlement policy at a proper price. An auction system between a seller and a bidder via a communication network constructed to calculate a proper price of a viatical and life settlement policy based on an insured, a estimated remaining life of the insured calculated by a doctor, an insurance due to be paid by the insured, a commission fee of an investment trust institution and the annual interest of a viatical and life settlement policy so that it is possible to prevent the viatical and life settlement policy from being set at an illegally low price and for the insured to sell the life settlement policy at an optimized market price while fairness of a trade is maintained.

Abstract: The present invention enables a CPU to access a SRAM in the shortest time in sync with the SRAM's ready timing, resulting in a reduction of avarage system boot-up time. The present invention is a processor boot-up controller that includes: volatile memory, which is connected to nonvolatile memory; a selector, which transfers boot-up codes to the volatile memory from the nonvolatile memory; a controller for the nonvolatile memory which is configured from a boot-up control sequencer, which transmits CPU read-in data to the CPU and brings the CPU into a wait state until boot-up code transfer completes; and an error detection and correction unit; is connected to the external CPU and the nonvolatile memory, and boot-up controls the CPU by reading data from the nonvolatile memory. The present invention is an information processing system using a controller for nonvolatile memory, a microprocessor boot-up controller, and multi-valued nonvolatile memory.