Abstract: A semiconductor integrated circuit device has a plurality of functional blocks. Each of the plurality of functional blocks comprises a DLL circuit for outputting a clock signal, at least one wiring portion for receiving the clock signal at one end thereof, and at least one load circuit for receiving the clock signal from the DLL circuit via the wiring portion. The DLL circuit receives a reference clock signal and a wiring portion and outputs the clock signal so that the phase difference between the reference clock signal and the second clock signal is a predetermined value. Thus, clock skew is reduced even if there is variation due to process.

Abstract: An ATM switch having multiple input and output ports is provided. The ATM switch receives ATM cells through the input ports and outputs the ATM cells through one of the output ports in accordance with output port information included in the ATM cells. An output buffer is also provided for each of the output ports to store ATM cells to be output through the output port. A cell counter is provided for each of the output buffers to count the number of ATM cells being stored in the output buffer. Additionally, the ATM switch includes counter verification circuitry for determining whether the cell counters are correctly counting the number of ATM cells stored in the output buffers.

Abstract: In an ATM cell processing device having a data transfer LSI capable of transferring ATM cells, and receiver LSIs capable of receiving the ATM cells having a same content, each data receiver LSI has a data input buffer, a data output buffer connected to the output side of the data input buffer and the input side of the data input buffer is connected to the output side of the data output buffer in the preceding data receiver LSI, and the output side of the data output buffer is connected to the input side of the data input buffer in the following data receiver LSI to form a data transfer path having a cascade connection so that the data of a same content transferred from the data transfer LSI is received in each of the data receiver LSIs in order.

Abstract: An image processor, including a housing having a transparent plate disposed on the upper surface thereof, and a swing frame pivotally mounted on the housing. In the swing frame is disposed a document conveyer which includes document suppressing rollers. In a state where the swing frame is brought to the closed position, the document suppressing rollers extend over the transparent plate, maintaining a space relative thereto in the direction of width of the transparent plate. A first shaft member is mounted on the swing frame, a pair of support brackets are rotatably mounted on the first shaft member separated by a distance in the axial direction, a second shaft member is mounted on the pair of support brackets to extend in the direction of width of the transparent plate in a state where the swing frame is brought to the closed position, and the document suppressing rollers are mounted on the second shaft member.

Abstract: The number of registers allocated to each register window (module) is stored in the memory means. The registers, constituting each module are determined by the number allocated in the memory means. Namely, in accordance with individual procedures in the program, a working register used on that procedure is determined and the number of registers constituting the working register is determined.In addition, memorization of the number of registers allocated to each register window in the memory means is automatically carried out on the basis of address information for a working register. Alternatively, memorization of the number of allocation is carried out on the basis of one of the instructions that the CPU can execute.

Abstract: A digital phase-locked loop (DPLL) circuit, which achieves a high-precise phase matching between input and output clocks at high speed, irrespective of phase difference between both, is disclosed.

Abstract: A unit cell switch includes a plurality of input communication routes and output communication routes for transferring data cells therebetween, a plurality of first conversion devices for converting each cell given from these input communication routes into a desired form, a plurality of second conversion devices for converting each data given from the first conversion devices into a suitable form and transferring the resultant data to one of these output communication routes. Cell storing devices respectively receive and temporarily store cells transferred from corresponding first conversion devices based on address information given to the cells.

Abstract: An information processing apparatus which includes a main memory for storing a plurality of data blocks each having a predetermined size stores a plurality of data blocks. Each data block includes a plurality of words, and each word includes a plurality of byte data. A data memory section in a cache memory for storing a small amount of data as compared with that of the main memory to achieve high-speed processing transfers data from/to the main memory in units of data blocks. A microprocessor generates a request address including desired data block and word addresses in order to access a plurality of desired words in a desired data block in the data memory section. A comparator determines whether a data block corresponding to the data block address is present in the data memory section. The microprocessor reads a plurality of words corresponding to the word address in the plurality of words in the corresponding data block from the data memory section in response to an output from the comparator.

Abstract: A multiport RAM comprises a memory section formed of many unit memory cells which are positioned to an orderly matrix of M columns by N rows, a write address designation section for designating the unit memory cells on the prescribed rows, a write clock signal by which the input data is synchronized in the write operation that the data is written in the unit memory cells designated by the write address designation section, a read address designation section for designating the unit memory cells on one or more prescribed rows, and a read clock signal by which the output data is synchronized in the read operation that the data is read out from the unit memory cells designated by the read address designation section, having no relation with the write private clock signal.

Abstract: A semiconductor integrated circuit comprises an Emitter Coupled Logic (ECL) input buffer and an ECL output buffer which are driven by m (m is equal to 2 or more) power supplies, a test ECL input buffers and a test ECL output buffers which are driven by m power supplies, and four first to fourth drive voltage supply lines for delivering drive voltages to the four input and output buffers.

Abstract: A paper feeding device for a paper cassette of an image processing apparatus. The paper cassette is mounted at a specific position or the image processing apparatus in a manner permitting the cassette to be pulled out. A preliminary feed roller feeds the paper on the paper cassette toward a feed roller which is normally energized in a paper pressing direction. When the paper cassette is mounted in the image processing apparatus, the document setting board disposed in the paper cassette is upwardly turned by a pressing mechanism. When the paper cassette is pulled out, the feed roller from the paper cassette is turned in reverse direction. A feed channel to guide the paper from the paper cassette is formed in a curved manner, and a normally turned delivery roller is provided inside the curved channel.

Abstract: A paper feeding device for a paper cassette of an image processing apparatus. The paper cassette is mounted at a specific position on the image processing apparatus in a manner permitting the cassette to be pulled out. A preliminary feed roller feeds the paper on the paper cassette toward a feed roller which is normally energized in a paper pressing direction. When the paper cassette is mounted in the image processing apparatus, the document setting board disposed in the paper cassette is upwardly turned by a pressing mechanism. When the paper cassette is pulled out, the feed roller from the paper cassette is turned in reversed direction. A feed channel to guide the paper from the paper cassette is formed in a curved manner, and a normally turned delivery roller is provided inside the curved channel.

Abstract: An image processing machine functions both as a facsimile machine and as an ordinary copying machine. The image processing machine is provided with a document scanning system and image-forming system. The document scanning system comprises a first scanning zone, a second scanning zone an image-receiving system, an optical system for optically connecting the first scanning zone and the second scanning zone to the image-receiving system, a first document scan moving system for moving a document across the first scanning zone and a second document scan moving system for moving a document across the second scanning zone. The image-forming system comprises printing system with a print output zone and a system for conveying a printing substrate through the printing output zone. An ink ribbon cartridge in the image forming system has a detector for detecting a broken ink ribbon.

Abstract: A paper feeding device having a document tray attached to a specified position of an image processing apparatus, a paper cassette mounted onto a specific position in the image processing apparatus in a manner that can be pulled out, and a preliminary feed roller to carry the paper set on the document tray toward a feed roller which is normally energized in paper pressing direction. When a sheet of paper is inserted, the preliminary feed roller is moved in the opposite direction against the energizing force under a balanced condition in transversal direction by a guide member which is turned upward. When the paper cassette is mounted in the image processing apparatus, the document setting board disposed in the paper cassette is upwardly turned by a pressing mechanism. When the paper cassette is pulled out, the feed roller to feed out paper from the paper cassette is turned in reversed direction.

Abstract: A CMOS logic circuit includes a first MOS transistor of one conductivity type and second and third MOS transistors of a conductivity type opposite to that of the first MOS transistor, the first to third MOS transistors being conducted in series with each other between first and second power source terminals. The gate of the first MOS transistor and the gate of one of the second and third MOS transistors commonly receive a input signal. The gate of the other of the second and third MOS transistors, serving as a correcting transistor, is connected to the first power source terminal. A series connecting point of the first and second MOS transistors serves as an output node. A channel size ratio W/L (where W is the channel width and L is the channel length) or an absolute value of a gate threshold voltage of the first MOS transistor is different from that of the correcting transistor.