Patents by Inventor Kenji Sasaki

Kenji Sasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190058054
    Abstract: On a single-crystal semiconductor substrate with an upper surface including a first direction in which an inverted mesa step extends and a second direction in which a forward mesa step extends in response to anisotropic etching in which an etching rate depends on crystal plane orientation, a bipolar transistor including a collector layer, a base layer, and an emitter layer that are epitaxially grown, and a base wire connected to the base layer are arranged. A step is provided at an edge of the base layer, and the base wire is extended from inside to outside of the base layer in a direction intersecting the first direction in a plan view. An intersection of the edge of the base layer and the base wire has a disconnection prevention structure that makes it difficult for step-caused disconnection of the base wire to occur.
    Type: Application
    Filed: August 8, 2018
    Publication date: February 21, 2019
    Inventors: Kenji SASAKI, Yasuhisa Yamamoto
  • Patent number: 10211364
    Abstract: A surface mount emissive element is provided with a top surface and a bottom surface. A first electrical contact is formed exclusively on the top surface, and a second electrical contact is formed exclusively on the top surface. A post extends from the bottom surface. An emissive display is also provided made from surface mount emissive elements and an emissions substrate. The emissions substrate has a top surface with a first plurality of wells formed in the emissions substrate top surface. Each well has a bottom surface, sidewalls, a first electrical interface formed on the bottom surface, and a second electrical interface formed on the bottom surface. The emissions substrate also includes a matrix of column and row conductive traces forming a first plurality of column/row intersections, where each column/row intersection is associated with a corresponding well. A first plurality of emissive elements populates the wells.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: February 19, 2019
    Assignee: eLux, Inc.
    Inventors: Paul J. Schuele, Kenji Sasaki, Kurt Ulmer, Jong-Jan Lee
  • Publication number: 20190051645
    Abstract: A semiconductor device includes a sub-collector layer disposed on a substrate, a bipolar transistor including a collector layer formed of a semiconductor having a lower carrier concentration than the sub-collector layer, a base layer, and an emitter layer, and a protection diode including a Schottky electrode. The Schottky electrode forms, in a partial region of an upper surface of the collector layer, a Schottky junction to the collector layer and is connected to one of the base layer and the emitter layer. In the collector layer, a part that forms a junction to the base layer and a part that forms a junction to the Schottky electrode are electrically connected to each other via the collector layer.
    Type: Application
    Filed: July 17, 2018
    Publication date: February 14, 2019
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Kenji SASAKI, Isao OBU
  • Patent number: 10203583
    Abstract: Disclosed herein is an optical waveguide element that includes a substrate and a waveguide layer formed on the substrate and comprising lithium niobate. The waveguide layer has a slab part having a predetermined thickness and a ridge part protruding from the slab part. The maximum thickness of the slab part is 0.05 times or more and less than 0.4 times a wavelength of a light propagating in the ridge part.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: February 12, 2019
    Assignee: TDK CORPORATION
    Inventors: Shinji Iwatsuka, Kenji Sasaki, Satoshi Shirai
  • Patent number: 10192862
    Abstract: An amplifier circuit including a semiconductor element is formed on a substrate. A protection circuit formed on the substrate includes a plurality of protection diodes that are connected in series with each other, and the protection circuit is connected to an output terminal of the amplifier circuit. A pad conductive layer at least partially includes a pad for connecting to a circuit outside the substrate. The pad conductive layer and the protection circuit at least partially overlap each other in plan view.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: January 29, 2019
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kenji Sasaki, Takayuki Tsutsui, Isao Obu, Yasuhisa Yamamoto
  • Publication number: 20190011872
    Abstract: A cleaning blade 1 includes an elastic body 11 that is a molded body of a rubber base material, and which has at least a surface treatment layer 12 in a portion of the elastic body 11, the portion coming into contact with an object to be contacted. The surface treatment layer 12 is formed by impregnating a surface portion of the elastic body 11 with a surface treatment liquid, which contains an isocyanate compound and an organic solvent, and curing the surface treatment liquid; the surface treatment layer 12 has an elastic modulus of 95 MPa or less; the elastic body 11 has an elastic modulus of from 20 MPa to 60 MPa (inclusive); and the difference between the elastic modulus of the surface treatment layer 12 and the elastic modulus of the elastic body 11 is 1 MPa or more.
    Type: Application
    Filed: December 22, 2016
    Publication date: January 10, 2019
    Applicants: NOK CORPORATION, SYNZTEC CO., LTD.
    Inventors: Syo KAWABATA, Kenji SASAKI, Yasushi SUGIYAMA, Hiroaki KANEDA, Natsumi KIMURA, Katsuya SHIMOTSUMA, Koji NISHIGUCHI, Shuji ABE, Hidetomo MUKAI
  • Publication number: 20190006564
    Abstract: A method is provided for fabricating an encapsulated emissive element. Beginning with a growth substrate, a plurality of emissive elements is formed. The growth substrate top surface is conformally coated with an encapsulation material. The encapsulation material may be photoresist, a polymer, a light reflective material, or a light absorbing material. The encapsulant is patterned to form fluidic assembly keys having a profile differing from the emissive element profiles. In one aspect, prior to separating the emissive elements from the handling substrate, a fluidic assembly keel or post is formed on each emissive element bottom surface. In one variation, the emissive elements have a horizontal profile. The fluidic assembly key has horizontal profile differing from the emissive element horizontal profile useful in selectively depositing different types of emissive elements during fluidic assembly.
    Type: Application
    Filed: September 8, 2018
    Publication date: January 3, 2019
    Inventors: Kenji Sasaki, Paul J. Schuele
  • Publication number: 20190006994
    Abstract: A power amplifier circuit includes a first amplifier transistor and a bias circuit. The first amplifier transistor amplifies a first signal and outputs a second signal. The bias circuit supplies a bias voltage or a bias current to the first amplifier transistor. The first amplifier transistor includes plural unit transistors disposed in a substantially rectangular region. The bias circuit includes first and second bias transistors and first and second voltage supply circuits. The first and second bias transistors respectively supply first and second bias voltages or first and second bias currents to the bases of unit transistors of first and second groups. The first and second voltage supply circuits respectively supply first and second voltages to the bases of the first and second bias transistors. The first and second voltages are decreased in accordance with a temperature increase. The second voltage supply circuit is disposed within the substantially rectangular region.
    Type: Application
    Filed: August 21, 2018
    Publication date: January 3, 2019
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventor: Kenji SASAKI
  • Patent number: 10170664
    Abstract: A surface mount emissive element is provided with a top surface and a bottom surface. A first electrical contact is formed exclusively on the top surface, and a second electrical contact is formed exclusively on the top surface. A post extends from the bottom surface. An emissive display is also provided made from surface mount emissive elements and an emissions substrate. The emissions substrate has a top surface with a first plurality of wells formed in the emissions substrate top surface. Each well has a bottom surface, sidewalls, a first electrical interface formed on the bottom surface, and a second electrical interface formed on the bottom surface. The emissions substrate also includes a matrix of column and row conductive traces forming a first plurality of column/row intersections, where each column/row intersection is associated with a corresponding well. A first plurality of emissive elements populates the wells.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: January 1, 2019
    Assignee: eLux, Inc.
    Inventors: Paul J. Schuele, Kenji Sasaki, Kurt Ulmer, Jong-Jan Lee
  • Publication number: 20180358933
    Abstract: A power amplifier circuit is capable of restraining uneven temperature distribution among a plurality of unit transistors while restraining the deterioration of the characteristics of the power amplifier circuit. The power amplifier circuit includes: a first transistor group which includes a plurality of unit transistors and which amplifies an input signal and outputs an amplified signal; a bias circuit which supplies a bias current or a bias voltage to a base or a gate of each unit transistor of the first transistor group; a plurality of first resistive elements, each of which is connected between the base or the gate of each unit transistor of the first transistor group and an output of the bias circuit; and a plurality of second resistive elements, each of which is connected between an emitter or a source of each unit transistor of the first transistor group and a reference potential.
    Type: Application
    Filed: June 7, 2018
    Publication date: December 13, 2018
    Inventors: Toshiki MATSUI, Kenji SASAKI, Fumio HARIMA
  • Patent number: 10151393
    Abstract: A metal gasket material plate includes a sealing layer formed by layering a chemical coating layer, an adhesive layer, and a rubber coating layer in this order on at least one side of a metal plate. The chemical coating layer is formed by a thermosetting surface preparation agent including inorganic compound particles and a metal alkoxide compound. The adhesive layer is formed by an adhesive including an epoxy compound and an anti-corrosive pigment. The rubber coating layer is formed by a rubber agent including rubber.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: December 11, 2018
    Assignees: NIPPON LEAKLESS INDUSTRY CO., LTD., HONDA MOTOR CO., LTD.
    Inventors: Satoshi Ota, Naomichi Mitsuyama, Yosuke Yoshizawa, Yuji Mitsumori, Kenji Sasaki, Masayuki Nakamura, Akihiro Okubo, Akira Masukura, Noriyuki Kitagawa
  • Patent number: 10146671
    Abstract: Methods, computer program products, and systems are presented. There can be provided inputting a set of test transactions into a shadow production system, wherein providing of a set of test transactions includes modifying of a set of transactions of a production system, and obtaining a result of the inputting.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: December 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Seiei Fujiwara, Kazumasa Kawaguchi, Reona Kondoh, Kenji Sasaki, Hiroshi Yoshioka
  • Patent number: 10128797
    Abstract: A power amplifier circuit includes a first amplifier transistor and a bias circuit. The first amplifier transistor amplifies a first signal and outputs a second signal. The bias circuit supplies a bias voltage or a bias current to the first amplifier transistor. The first amplifier transistor includes plural unit transistors disposed in a substantially rectangular region. The bias circuit includes first and second bias transistors and first and second voltage supply circuits. The first and second bias transistors respectively supply first and second bias voltages or first and second bias currents to the bases of unit transistors of first and second groups. The first and second voltage supply circuits respectively supply first and second voltages to the bases of the first and second bias transistors. The first and second voltages are decreased in accordance with a temperature increase. The second voltage supply circuit is disposed within the substantially rectangular region.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: November 13, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Kenji Sasaki
  • Publication number: 20180262167
    Abstract: A semiconductor device includes a semiconductor substrate having a principal surface which has a first side in a first direction and a second side in a second direction. A plurality of transistor arrays is formed in a region adjacent to the first side of the semiconductor substrate. A plurality of bumps include first and second bumps which are longer in the first direction. The distance between the first side and the first bump is shorter than the distance between the first side and the second bump. The plurality of transistor arrays include a first and a second transistor arrays. The first transistor array has a plurality of first unit transistors arranged along the first direction such that the first unit transistors overlap the first bump. The second transistor array has a plurality of second unit transistors arranged along the first direction such that the second unit transistors overlap the second bump.
    Type: Application
    Filed: May 10, 2018
    Publication date: September 13, 2018
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Kenji SASAKI, Kenichi SHIMAMOTO
  • Publication number: 20180247926
    Abstract: An amplifier circuit including a semiconductor element is formed on a substrate. A protection circuit formed on the substrate includes a plurality of protection diodes that are connected in series with each other, and the protection circuit is connected to an output terminal of the amplifier circuit. A pad conductive layer at least partially includes a pad for connecting to a circuit outside the substrate. The pad conductive layer and the protection circuit at least partially overlap each other in plan view.
    Type: Application
    Filed: February 22, 2018
    Publication date: August 30, 2018
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Kenji SASAKI, Takayuki TSUTSUI, Isao OBU, Yasuhisa YAMAMOTO
  • Patent number: 10059800
    Abstract: A method of producing a polycarbonate, including: introducing a tertiary amine into a reaction process; and performing interfacial polycondensation between an alkali aqueous solution of a dihydric phenol and phosgene in the presence of an organic solvent, in which: (i) a portion into which the tertiary amine is introduced comprises at least a tertiary amine storage tank, a tertiary amine supply pipe, and a diluent solvent supply pipe; (ii) the portion further includes a pressure control valve in the tertiary amine supply pipe on an upstream side of a merging portion with the diluent solvent supply pipe; and (iii) when a pressure P1 of an inside of the tertiary amine storage tank pressurized by a pressurization gas and a pressure P2 in a portion ranging from an outlet of the storage tank to an upstream side of the pressure control valve, a relationship of P1?P2 is satisfied.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: August 28, 2018
    Assignee: IDEMITSU KOSAN CO., LTD.
    Inventors: Kenji Sasaki, Masayuki Takahashi, Hiroaki Motegi
  • Publication number: 20180219138
    Abstract: Fluidic assembly methods are presented for the fabrication of emissive displays. An emissive substrate is provided with a top surface, and a first plurality of wells formed in the top surface. Each well has a bottom surface with a first electrical interface. Also provided is a liquid suspension of emissive elements. The suspension is flowed across the emissive substrate and the emissive elements are captured in the wells. As a result of annealing the emissive substrate, electrical connections are made between each emissive element to the first electrical interface of a corresponding well. A eutectic solder interface metal on either the substrate or the emissive element is desirable as well as the use of a fluxing agent prior to thermal anneal. The emissive element may be a surface mount light emitting diode (SMLED) with two electrical contacts on its top surface (adjacent to the bottom surfaces of the wells).
    Type: Application
    Filed: March 21, 2018
    Publication date: August 2, 2018
    Inventors: Kenji Sasaki, Paul J. Schuele, Kurt Ulmer, Jong-Jan Lee
  • Publication number: 20180219139
    Abstract: Fluidic assembly methods are presented for the fabrication of emissive displays. An emissive substrate is provided with a top surface, and a first plurality of wells formed in the top surface. Each well has a bottom surface with a first electrical interface. Also provided is a liquid suspension of emissive elements. The suspension is flowed across the emissive substrate and the emissive elements are captured in the wells. As a result of annealing the emissive substrate, electrical connections are made between each emissive element to the first electrical interface of a corresponding well. A eutectic solder interface metal on either the substrate or the emissive element is desirable as well as the use of a fluxing agent prior to thermal anneal. The emissive element may be a surface mount light emitting diode (SMLED) with two electrical contacts on its top surface (adjacent to the bottom surfaces of the wells).
    Type: Application
    Filed: March 21, 2018
    Publication date: August 2, 2018
    Inventors: Kenji Sasaki, Paul J. Schuele, Kurt Ulmer, Jong-Jan Lee
  • Patent number: 10030101
    Abstract: Provided is a method of producing a branched polycarbonate, including: a step (a) of subjecting an alkali aqueous solution of a dihydric phenol, phosgene, and a branching agent to a phosgenation reaction in the presence of an organic solvent to provide a reaction liquid; a step (b) of adding the alkali aqueous solution of the dihydric phenol and a polymerization catalyst to the reaction liquid obtained from the step (a) to provide a reaction liquid containing a polycarbonate oligomer; a step (c) of separating the reaction liquid containing the polycarbonate oligomer obtained in the step (b) into an organic solvent phase containing the polycarbonate oligomer and an aqueous phase; and a step (d) of causing the organic solvent phase containing the polycarbonate oligomer separated in the step (c) and the alkali aqueous solution of the dihydric phenol to react with each other to provide a reaction liquid containing the branched polycarbonate, in which a ratio (x/y) of an addition amount of the polymerization catal
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: July 24, 2018
    Assignee: IDEMITSU KOSAN CO., LTD.
    Inventors: Noriyuki Kunishi, Kazuhiro Sekiguchi, Yukiko Nagao, Masayuki Takahashi, Kenji Sasaki
  • Patent number: 10018956
    Abstract: A cleaning blade has an elastic body formed of a urethane elastomer, and a treated surface layer formed at least at a portion which comes into contact with a contact target of the elastic body. The treated surface layer is formed through impregnating a surface portion of the elastic body with a surface treatment liquid containing a bifunctional isocyanate compound, at least one polyol, and an organic solvent; or a surface treatment liquid containing an isocyanate group-containing compound having an isocyanate group at an end thereof, which compound is a reaction product of the bifunctional isocyanate compound with the at least one polyol, and an organic solvent, and curing the surface treatment liquid. The difference between the nitrogen concentration at the surface and the nitrogen concentration in the elastic body at a depth of 0.5 mm from the surface of the treated surface layer is 0.02 to 0.15 mass %.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: July 10, 2018
    Assignees: NOK CORPORATION, SYNZTEC CO., LTD.
    Inventors: Syo Kawabata, Kenji Sasaki, Katsumi Abe, Natsumi Kimura